JPS60201718A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To prevent a malfunction when a power supply has a short break by connecting a capacitor in parallel to a base resistance of one of both transistors of an FF circuit and supplying the complementary output of the FF circuit to a differential amplifier connected with a discharging transistor and a capacitor through an input terminal at one side. CONSTITUTION:When a set signal is supplied to an input terminal 3, an output terminal 5 is set at an H level by an FF action. At the same time, a capacitor 14 is charged by the base current of a TR7. While a capacitor 24 is discharged when TR17, 19 and 23 of a differential amplifier are turned on. Here the power supply voltage is reduced by noises and each TR is cut off and then reset. In such a case, the TR7 is first turned on by the speed-up capacitor 14 to set the output of the TR14 under a state set before a short break of the power supply. While an output 5 is set an L state in a reset mode and the power supply has a short break. Thus the base current of a TR8 flows via a resistance 10 by the charged electric charge of the capacitor 24 to reset a state set before the short break.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a flip-flop circuit used in a place where noise is likely to occur.

(Prior art) Conventionally, an Aritz flop circuit has a circuit configuration as shown in FIG. has been done. Transistor 6 is connected in parallel with transistor 7, and has its base connected to set signal input terminal 3. The base of transistor 7 is connected to output terminal 5 via resistor 11. Output terminal and ground line 1
Transistors 8 and 9 are connected in parallel between them.
The base of transistor 80 is connected to the collectors of transistors 6 and 7 via resistor 10. transistor 9
A signal input terminal 4 is connected to the base of the circuit. Here, the base voltage of each transistor is as shown in FIG. If the lightning or potential difference between power line 2 and ground line 1 is stable, there will be no problem with the operation of this flip-flop circuit, but in cases such as automotive electrical components, noise from ignition sparks may The potential of the ground line 1 may drop to around the level 1 of the ground line 1, cutting off the transistors 6 to 9. In this case, even if the power supply line 2 returns to its original level, if the set signal or reset signal does not enter the base of the transistor 6 or the base of the transistor 90, whichever of the transistors 7 or 8 becomes conductive first. Since the output 5 of the flip-flop circuit is not determined uniquely, a malfunction may occur.

(Object of the Invention) An object of the present invention is to provide a flip-flop circuit with excellent noise resistance for use in IC circuits and the like used in places where noise is likely to occur.

(Yang Cheng 1 operation and effect of the present invention) According to the present invention, the collectors of the first and second transistors are connected to each other, and the base of the first transistor is connected to the collector of the second transistor. a first resistor connecting the base of the second transistor to the collector of the first transistor;
a first capacitive element connected in parallel to the resistor, a second capacitive element connected between the collector of the first transistor and a reference potential, and an emitter that receives current from the collector output of the second transistor. A third transistor is connected to the power supply terminal through the current source, and a third transistor whose base receives the collector output of the first transistor and whose emitter is connected to the power supply terminal through the aforementioned current source. The $4 transistor that makes up the dynamic amplifier and the collector
A flip 70-tube circuit is obtained which includes a fifth transistor whose emitter is connected in parallel to the second capacitive element and whose base receives the collector output of the fourth transistor.

In the flip-flop circuit of the present invention, the first capacitive element is
In the set state, even if the power supply drops to ground potential and each transistor is cut off.

It acts as a speed-up capacitor and makes the first transistor conductive when the power supply is turned off. Furthermore, even if the power supply fluctuates in the reset state and each transistor is cut off, the second capacitive element is filled with charge and acts to make the second transistor conductive. In this way, the two capacitive elements can prevent the flip-flop circuit from malfunctioning due to instability of the power supply line.

(Example of the invention) Next, the present invention will be described in more detail with reference to the compartments.

FIG. 3 is a circuit diagram according to an embodiment of the present invention.

A normal 7-lip flop consisting of transistors 6 to 9, etc., capacitors 4 and 24 and transistors 16 to 19°
and a resistor 20 which is its load.
, 21 and transistors 22 and 23 are added. In normal operation, when a set signal is input to the set signal input terminal 3, the transistor 6 becomes conductive and the transistor 8 is cut off. Therefore, if the reset signal is not input to the reset signal input terminal 4, the transistors 8 and 9
The collector of becomes high potential and makes the transistor 7 conductive, and even if the set signal disappears and the transistor 6 is cut on, the transistor 7 maintains the conductive state.
Its collector voltage remains low and transistor 8 remains cut off. Therefore, the output terminal 5 is maintained at a high potential. Conversely, if a reset code is input to the reset code input terminal 4 in this state, the transistor 9 becomes conductive, so the collector voltage becomes low potential and the transistor 7 is cut off.

Therefore, the collector voltage of the transistor 6.7 becomes a high potential, making the transistor 8 conductive, and even if the reset signal is lost, the output terminal 5 is maintained at a low potential.

In this circuit, if a situation occurs in which noise enters, power line 2 becomes unstable, and each transistor cuts on, first, if the set signal is input and the output is at a high potential, each transistor In the state before cut-on, the transistors 17 and 19 of the comparator made up of transistors 16 to 19 are in a conductive state, and the capacitor 24 is discharged, so that almost no charge is accumulated. When the power supply voltage is restored in this state, the speed-up capacitor 14 is charged first by the capacitor 24, and the collector voltages of transistors 8 and 9 are brought to a high potential, transistor 7 is made conductive, and the output is maintained at a high potential. . Conversely, when the reset signal is input, the capacitor 24 is charged to a high potential, so even if each transistor is cut off, the charged charge passes through the base resistor lo and flows to the base of the transistor 8. The current flows, making the transistor 8 conductive and keeping the output at a low potential. Fourth
The figure shows an example in which the comparator is composed of two transistors.

In this way, the Aritub flop circuit of the present invention can prevent malfunctions even when used in places where there is a lot of noise, such as automotive electrical equipment.

Also, in order to maintain memory, it is common to attach large capacity capacitors on both the set and reset sides.
In the circuit of the present invention, only one capacitor 240 with a large capacity is required. When the circuit is configured with a monolithic IC, one capacitor 14 can be made inside the IC, reducing the number of external parts and improving reliability. was able to increase.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional 7-lip-flop circuit, m2
3 is a circuit diagram of a flip-flop circuit according to one embodiment of the present invention, and FIG. 4 is a circuit diagram of a flip-flop circuit according to another embodiment of the present invention.

Claims (1)

[Scope of Claims] First and second transistors whose collectors are connected to a power supply line via respective loads, and a transistor connected between the base of the first transistor and the collector of the second transistor; a parallel circuit of a first resistor and a first capacitor; a second resistor connected between the base of the second transistor and the collector of the first transistor;
a second capacitor connected between the collector of the first transistor and a reference potential; a base connected to the collector of the second transistor; and an emitter connected to the power supply line via a current source. a third transistor, the base of which is connected to the collector of the first transistor;
A fourth transistor whose emitter is connected to the power supply line through a current source, and a fifth transistor whose emitter-collector is connected in parallel to the second capacitor and whose base receives the collector output of the fourth transistor. A flip-flop circuit comprising a transistor.