JPH0317251B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a frequency-controlled oscillation circuit that generates a signal having an arbitrary multiple of a frequency from a signal having a stable frequency.

[Technical background of the invention and its problems]

Recently, devices that perform speech synthesis using digital technology have been developed and put into practical use. In this device, for example, an impulse or white noise is used as a sound source, and the signal from this sound source is passed through several digital filter circuits to obtain an analog audio signal. The conditions for each digital filter circuit are set in accordance with the analog audio signal to be obtained at that time. Further, the conditions for each digital filter circuit in the digital speech synthesizer are set based on the results of analyzing and recognizing actual speech.

FIG. 1 is a circuit diagram showing a general configuration of a speech recognition circuit that performs the above-mentioned speech recognition. In FIG. 1, 1 is a microphone amplifier. This microphone amplifier 1 is for amplifying an analog signal converted by a microphone (not shown).
The output of the microphone amplifier 1 is transmitted through, for example, four bandpass filter circuits (BPF) 2A, 2B, 2C,
2D in parallel. Furthermore, the signals that have passed through the band pass filter circuits 2A, 2B, 2C, and 2D are sent to four detection circuits (DET) 3A, 3B,
3C and 3D, and each detection signal is sent to each of four low-pass filter circuits (LPF) 4.
It is supplied to A, 4B, 4C, and 4D. The signals that have passed through the low-pass filter circuits 4A, 4B, 4C, and 4D are selectively supplied to an analog/digital conversion circuit (A/D) 6 via a multiplexer (MPX) 5. The digital output from the analog/digital conversion circuit 6 becomes the recognition result for the input voice from the microphone.

By the way, in recent speech recognition circuits, high integration and high precision have been achieved by using switched capacitor filter technology, and the microphone amplifier 1, bandpass filter The circuit 2 and the low-pass filter circuit 4 are all constructed using switched capacitor circuits. A circuit using this switched capacitor circuit requires an oscillation circuit and a clock generation circuit for forming various clock pulses from the output of the oscillation circuit in order to control each switched capacitor circuit. Accuracy in switched capacitor circuits depends on the accuracy of the clock pulses used, and conventionally this clock pulse has been formed from the output of, for example, a CR oscillation circuit. However, this
Since the CR oscillation circuit has poor oscillation frequency accuracy, the accuracy of the switched capacitor circuit itself and, by extension, the speech recognition circuit deteriorates.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to utilize the oscillation signal of an oscillation circuit that stably oscillates using a crystal resonator etc. as a reference signal. The object of the present invention is to provide an oscillation circuit that can stably and accurately generate a signal having a frequency that is an arbitrary multiple from this reference signal.

[Summary of the invention]

In the oscillation circuit according to the present invention, the resistance value is set according to the oscillation output frequency of the Schmitt type oscillation circuit, and the resistance value is set according to the frequency of the negative switched capacitor circuit having a negative equivalent resistance and the reference signal. is set, a positive switched capacitor circuit having a positive equivalent resistance is provided, a constant DC voltage is supplied to one end of the negative switched capacitor circuit, and the positive switched capacitor circuit is supplied with a constant DC voltage to one end of the negative switched capacitor circuit. A DC voltage of a value corresponding to the frequency of the oscillation signal to be obtained is supplied to one end of the capacitor circuit, and the high level side of the Schmitt type oscillator circuit is A threshold voltage is set, thereby adjusting the frequency of the oscillation signal of the Schmitt oscillation circuit.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing the configuration of an embodiment of the oscillation circuit of the present invention. In the figure, 10 has a capacitor 11 and four switches 12 to 15, the resistance value of which is set according to the frequency _S of an oscillation signal S _S from a Schmitt type oscillation circuit, which will be described later.
It is a switched capacitor circuit (hereinafter abbreviated as SC circuit) that has a negative equivalent resistance. A switch 1 is connected to one end of the capacitor 11 in this SC circuit 10.
2 and 13 are connected to each other, and the other end of switch 12 is connected to a ground point. A switch 14 is connected to the other end of the capacitor 11.
and 15 are connected, and the other end of the switch 14 is connected to a ground point.
Of the four switches 12 to 15, two switches 12, 15 and 1 are selected respectively.
3 and 14 are alternately turned on in response to the signal S _S .

20 has a capacitor 21 and four switches 22 to 25, and a reference signal S _C with a stable frequency.
For example, this is an SC circuit in which the resistance value is set according to the frequency _C of the oscillation output signal S _C of an oscillation circuit using a crystal resonator, and has a positive equivalent resistance. One end of each of switches 22 and 23 is connected to one end of capacitor 21 in SC circuit 20, and the other end of switch 23 is connected to a ground point. One end of each of switches 24 and 25 is connected to the other end of the capacitor 21,
Further, the other end of the switch 25 is connected to a ground point. and the above four switches 22 to 2
2 switches 22, 24 each of 5
and 23, 25 are alternately turned on in response to the signal _SC .

The positive electrode side of the DC power supply V ₁ is connected to a point a to which the other end of the switch ₁₃ in the one SC circuit 10 is connected. The positive electrode side of the variable DC power supply V ₂ is connected to the two points a to which the other end of the switch ₂₂ in the other SC circuit 20 is connected. The negative electrode sides of the DC power supply V ₁ and the variable DC power supply V ₂ are both connected to a ground point. Further, the other end of the switch 15 in one SC circuit 10 is connected to the other end of the switch 24 in the other SC circuit 20, and the input end of the integrating circuit 30 is connected to this connection point b. . This integrating circuit 30 is for integrating the current flowing at the point b to obtain a voltage V _O having a value and polarity corresponding to the value and polarity of this current.

The integration circuit 30 includes a differential amplifier circuit 31 having an inverting input terminal, a non-inverting input terminal, and an output terminal.
and a capacitor 32.
2 is connected between the inverting input terminal and the output terminal of the differential amplifier circuit 31, and the non-inverting input terminal of the differential amplifier circuit 31 is connected to the ground point. The output voltage V _O of the integrating circuit 30 is supplied to a Schmitt oscillation circuit 50 via a voltage buffer circuit 40 .
The voltage buffer circuit 40 is composed of a differential amplifier circuit 41 having an inverting input terminal, a non-inverting input terminal, and an output terminal, the inverting input terminal and the output terminal are connected, and the voltage V _O is connected to the non-inverting input terminal. It has been entered.

A differential amplifier circuit 51 having a non-inverting input terminal, an inverting input terminal and an output terminal is provided within the Schmitt type oscillation circuit 50. The non-inverting input terminal of this differential amplifier circuit 51 has a high level side threshold voltage _VH and a low level side threshold voltage.
V _L is input alternately. The high level side threshold voltage V _H is determined by two resistors 52 connected in series between the positive polarity power supply voltage V _DD application point and the output terminal of the voltage buffer circuit 40 .
53 at the series connection point c, and this voltage V _H is P
Channel MOSFET54 and N channel
The signal is input to the non-inverting input terminal of the differential amplifier circuit 51 via a CMOS switch 56 consisting of a MOSFET 55. The threshold voltage V _L on the low level side is determined by the series connection point d of two resistors 57 and 58 connected in series between the above power supply voltage V _DD application point and the negative polarity power supply voltage V _SS application point. This voltage V _L is applied to a CMOS switch 61 consisting of a P channel MOSFET 59 and an N channel MOSFET 60.
The signal is input to the non-inverting input terminal of the differential amplifier circuit 51 via the differential amplifier circuit 51. The above differential amplifier circuit 5
Two inverters 62 and 63 are connected in cascade to the output terminal of No. 1, and the output terminal of the inverter 63 at the subsequent stage is
A resistor 64 and a capacitor 65 are connected to the V _SS application point.
are connected in series. The output signal of the inverter 63 at the latter stage is applied to the gate of the N-channel MOSFET 55 constituting the CMOS switch 56 and
P channel configuring CMOS switch 61
It is input in parallel to the gate of MOSFET 59 and also to two inverters 66 and 67. The output signal of the inverter 66 is
P channel configuring CMOS switch 56
Gate of MOSFET54 and CMOS switch 6
It is input in parallel to the gate of an N-channel MOSFET 60 constituting the MOSFET 1. In addition, the resistor 64
The voltage at the series connection point e between the capacitor 65 and the capacitor 65 is input to the inverting input terminal of the differential amplifier circuit 51.
The output signal of the inverter 67 is supplied to other circuits as the oscillation output signal S _S of this oscillation circuit, and this signal S _S is fed back to the one SC circuit 10 .

Furthermore, the three differential amplifier circuits 31, 41, and 51 provided in this embodiment circuit have a power supply voltage of positive polarity V _DD and a power supply voltage of negative polarity V _SS having the same absolute value as this V _DD . The potential of the ground point is between the two voltages V _DD and
It is set to OV, which is an intermediate potential with V _SS .

In the circuit having the above configuration, first, the operation of the Schmitt type oscillation circuit 50 will be explained. Now, the threshold voltage V _H obtained at point c is fixed in advance according to the resistance ratio of the resistors 52 and 53 and the output voltage V _O from the voltage buffer circuit 40, and this voltage V _H is , 58 is higher than the threshold voltage V _L obtained at point d. When the output signal of the differential amplifier circuit 51 is now at a high level (V _DD level), the output signal of the inverter 63 is also set to a high level, so the capacitor 65 is connected to the resistor 64 and the capacitor 65 via the resistor 64. It is charged with a time constant τ depending on the value of . Therefore, the voltage at point e gradually increases. On the other hand, when the output signal of the inverter 63 is at a high level, the CMOS switch 56 is turned on, and the high level side signal is connected to the non-inverting input terminal of the differential amplifier circuit 51 via this CMOS switch 56. Threshold voltage V _H is input. Therefore, the differential amplifier circuit 51 compares this threshold voltage _VH with the voltage at the point e. When the voltage at point e reaches the threshold voltage _VH ,
The output signal of the differential amplifier circuit 51 is inverted from high level to low level (V _SS level). After this level inversion, the output signal of the inverter 63 is also inverted to a low level, so the capacitor 65, which has been charged up to now, is now discharged to the V _SS level with a time constant τ via the resistor 64. Therefore, the voltage at point e now gradually decreases. On the other hand, when the output signal of the inverter 63 is at a low level, the CMOS switch 61 is turned on, and the non-inverting input terminal of the differential amplifier circuit 51 is connected to the CMOS switch 61.
A low-level threshold voltage V _L is inputted via the switch 61 . Therefore, at this time, the differential amplifier circuit 51 compares this threshold voltage V _L with the voltage at the point e. When the falling voltage at point e reaches the threshold voltage V _L , the output signal of the differential amplifier circuit 51 is inverted from low level to high level again. Similarly, the differential amplifier circuit 51 outputs the voltage at point e and the two threshold voltages.
By alternately comparing V _H and V _L , the output signal of the inverter 63 becomes an oscillation signal that alternately repeats a high level and a low level at a predetermined period. Furthermore, since the output signal S _S of the inverter 67 is an inverted signal of the inverter 63, this signal S _S also becomes an oscillation signal. And this Schmitt type oscillation circuit 50
The frequency _S of the oscillation signal S _S is constant when the threshold voltages V _H and V _L are set constant, and its value is a Schmitt value determined by the above threshold voltages V _H and V _L. It is made in accordance with the width (|V _H |+|V _L |) and the time constant τ determined by the values of the resistor 64 and capacitor 65. FIG. 3 is a waveform diagram showing the relationship between the voltage V _e at the point e and the output signal _S of the inverter 63.

On the other hand, the equivalent resistance value _R1 of the SC circuit 10 to which the oscillation signal S _S from the Schmitt type oscillation circuit 50 is input is given by the following equation, assuming that the value of the capacitor 11 is _C1 .

R ₁ = -1/C ₁・_S (1) Similarly, the equivalent resistance value R ₂ of the SC circuit 20 to which the signal S _C is input is given by the following formula, assuming that the value of the capacitor 21 is C ₂ It will be done.

R ₂ =1/C ₂・_C (2) Now, one end of each of the SC circuits 10 and 20, that is, the other end of the switch 13 in the SC circuit 10 and the SC
The other end of the switch 22 in the circuit 20 is connected to a DC power source.
Since a positive voltage is supplied from V ₁ or variable DC power supply V ₂ , DC current flows through both SC circuits 10 and 20, respectively. One SC circuit 10
has a negative equivalent resistance value R ₁ , so this SC circuit 1
The direction of the current I ₁ flowing through the current I 1 is toward the left in FIG. 2 (this is the direction of negative polarity). Since the other SC circuit 20 has a positive equivalent resistance value R ₂ , the direction of the current I ₂ flowing through this SC circuit 20 is to the right in FIG. 2 (this is defined as the positive polarity direction). That is,
The directions of the currents I ₁ and I ₂ are opposite to each other. The integrating circuit 30 is supplied with a combined current of both currents I ₁ and I ₂ . Now, when this composite current has a negative polarity, that is, when the current I ₁ is larger than I ₂ , the output voltage V _O of the integrating circuit 30 gradually increases toward the positive polarity power supply voltage V _DD . . Contrary to the above, when the combined current of currents I ₁ and I ₂ has positive polarity, that is, when I ₂ is larger than current I ₁ , the output voltage V _O of the integrating circuit 30 has negative polarity. The power supply voltage gradually decreases toward the power supply voltage V _SS . Then, while the output voltage V _O of the integrating circuit 30 is rising or falling, the output currents I ₁ and I ₂ of the SC circuits 10 and 20 reach an equilibrium state, and when the combined current becomes 0, the output voltage V _O changes. stops at that point, and then V _O
does not change.

Now suppose that the value of the DC power supply V ₁ and the value of the variable DC power supply V ₂ are set equal, and that the SC circuit 10,
It is assumed that the values C ₁ and C ₂ of capacitors 11 and 21 in 20 are set equal to each other. At this time,
In the SC circuits 10 and 20, when the frequencies S and _C of the two signals S _S and S _C match, the combined current of the currents _{I 1} and I ₂ is made 0, and the output voltage V _O of the integrating circuit 30 is Fixed to a value. When the value of V _O is fixed, the high-level threshold voltage V _H formed within the Schmitt oscillator circuit 50 is also fixed, thereby increasing the Schmitt width (|V _H | + | V _L | ) is also fixed, so the frequency _S of the oscillation signal S _S is also fixed.

From the state where the above frequencies _S and _C match, _S
Suppose that the As the frequency _S decreases, the above
The equivalent resistance value R ₁ of the SC circuit 10 given by equation (1) becomes larger than before, and thereby the absolute value of the current I ₁ becomes smaller. Then, the combined current of I ₁ and I ₂ becomes a positive value, and the output voltage V _O of the integrating circuit 30 becomes
Descend towards V _SS . As the voltage V _O drops toward V _SS , the Schmidt oscillator circuit 50
The voltage V _H obtained at point c in the Schmitt type oscillator circuit 50 decreases, and the Schmitt width (|V _H |+|V _L |) becomes narrower than before, so the frequency _S of the oscillation output signal S _S in the Schmitt type oscillator circuit 50 becomes Rise. As the frequency _S increases, the equivalent resistance value R ₁ of the SC circuit 10 becomes smaller, and the absolute value of the current I ₁ gradually becomes larger. Then, the combined current value of currents I ₁ and I ₂ decreases from positive polarity toward a value of 0, and becomes 0 when _S matches _C.
Therefore, when _S falls, the output voltage V _O of the integrating circuit 30 increases toward V _DD until it matches _C , and when V _O reaches its original value, the increase stops and the oscillation output signal S _S When the frequency _S of matches _C , the rise of _S also stops.

Assume that from the state where the frequencies _S and _C match, _S now increases. When the frequency _S increases, the equivalent resistance value R ₁ of the SC circuit 10 given by the above equation (1) becomes smaller than before, and the absolute value of the current I ₁ becomes larger. Then, the combined current of currents I ₁ and I ₂ has a negative polarity value, and the output voltage V _O of the integrating circuit 30
increases towards V _DD . As the voltage _VO increases,
The threshold voltage V _H on the high level side is higher than before, and the Schmitt width (|V _H | + | V _L |) is wider than before, so the Schmitt type oscillator circuit 50
The frequency _S of the oscillation output signal S _S decreases.
As the frequency _S decreases, the equivalent resistance value R ₁ of the SC circuit 10 increases, and the absolute value of the current I ₁ gradually decreases. Then, the combined current value of currents I ₁ and I ₂ increases from negative polarity toward the value of 0, and when _S matches _C , it becomes 0.
become. Therefore, when _S increases, the output voltage V _O of the integrating circuit 30 drops toward V _SS until it matches _C , and when V _O returns to its original value, the drop stops and the oscillation output signal S _S When the frequency _S of matches _C , the fall of _S also stops.

That is, in this example circuit, the DC power supply
When the value of V ₁ and the value of variable DC power supply V ₂ are set equal, and the values of capacitors 11 and 21 in SC circuits 10 and 20 are set equal to each other, the frequency of oscillation output signal S _{S S} is controlled to match the frequency _C of the signal _SC .

Next, the case of changing the setting of the variable DC power supply V ₂ will be explained. First, when V ₂ and V ₁ are set higher than V 1 , the output current I ₂ of this SC circuit 20 becomes larger than before because the equivalent resistance value R ₂ of the SC circuit 20 is constant. At this time, in order to balance the currents I ₁ and I ₂ and make the value of their combined current 0, the absolute value of the output current I ₁ of one SC circuit 10 needs to be larger than before.

As the current I ₂ increases, the output voltage V _O of the integrating circuit 30 drops toward V _SS , and then the oscillation output signal S _S of the Schmidt oscillator circuit 50
The frequency _S of increases. This increase in frequency _S continues until the absolute value of the output current I ₁ of the SC circuit 10 matches the absolute value of I ₂ . That is, when V ₂ is set higher than V ₁ , the frequency S of the oscillation output signal _{S S} is controlled to be constant at a point higher than _C.

Next, when V ₂ is set lower than V ₁ , the output current I ₂ of the SC circuit 20 becomes smaller than before. At this time, in order to balance the currents I ₁ and I ₂ and make their combined current value 0, contrary to the above, the absolute value of the output current I ₁ of one SC circuit 10 must be smaller than before. There is a need.

As the current I ₂ becomes smaller, the integration circuit 3
The output voltage V _O of 0 rises towards V _DD and after this,
The frequency _S of the oscillation output signal S _S of the Schmitt oscillation circuit 50 decreases. This decrease in frequency _S continues until the absolute value of the output current I ₁ of the SC circuit 10 matches the absolute value of I ₂ . That is, when V ₂ is set lower than V ₁ , the frequency _S of the oscillation output signal S _S is controlled to be constant at a point lower than _C.

By the way, the condition for stabilizing the oscillation frequency _S in this implementation condition circuit is that the two SC circuits 10, 2
The result is that the combined current value of the output currents I ₁ and I ₂ of 0 becomes 0. That is, this stability condition is given by the following equation.

I ₁ + I ₂ = 0 ......(3) The resistance value given by the above equations (1) and (2) in the above equation (3)
Substituting the relationship between R ₁ and R ₂ gives the following equation.

−C ₁ · _S · V ₁ +C ₂ · _C · V ₂ =0 (4) Next, when the above formula (4) is summarized for _S , the following formula is obtained.

_S = C ₂ /C ₁・V ₂ /V ₁・_C ………(5) Since we have assumed that C ₁ = C ₂ in advance, _S is _C multiplied by V ₂ /V ₁ becomes. Therefore, by adjusting the value of the variable DC power supply V ₂ , it is possible to create a signal S _S with a frequency _S that is an arbitrary multiple of _C.

Figure 4 shows a characteristic diagram of the above embodiment circuit when C ₁ = C ₂ , and the horizontal axis shows the oscillation signal S _S
The frequency _S is plotted on the vertical axis, and the value of the variable DC power supply V ₂ is plotted on the vertical axis. As shown in the figure, _S has a linear relationship with _V2 .

Here, the equivalent resistance values R ₁ and R 2 in the two SC circuits 10 and 20 are C 1 , R ₂ as shown in equations (1) and ( ₂ ) above,
If the value of C ₂ is constant, it is determined only by the frequencies _S and _C , and the values C ₁ and C ₂ of capacitors 11 and 21 can be set with much higher precision than resistors, etc., so the frequency _S , _C are resistors R ₁ with high precision,
converted to _R2 . The difference between the values of the resistors R ₁ and R ₂ is converted into a current, and this current is further converted into a voltage.
Since the oscillation frequency _S of is adjusted, this frequency _S
can be adjusted stably and with high precision.

Furthermore, in the above explanation, the oscillation frequency S is adjusted by changing the value of the variable DC power supply V ₂ , but as is clear from the above equation (4), this is done by adjusting the oscillation frequency _S by changing the value of the variable DC power supply V 2 . , ₂₀ can be changed to adjust the frequency to a _multiple according to the ratio. For example, by setting the values of capacitors 11 and 21 to satisfy the relationship n・C ₁ =C ₂ ,
The frequency of _S can be adjusted to n times that of _C.
Moreover, the value of n is not limited to an integer and can be set to a real number including a decimal, although this is also the case when changing the variable DC power supply _V2 . Further, V ₁ may be configured with a variable DC power supply instead of V ₂ .

FIGS. 5 and 6 are circuit diagrams specifically showing two SC circuits 10 and 20 used in the embodiment circuit, respectively. In FIGS. 5 and 6, parts corresponding to those in FIG. 2 are designated by the same reference numerals. Also, the signal
S _S and S _C are actually two-phase signals with different phases, as shown in the timing chart in Figure 7.
S _S1 , S _S2 or S _C1 , S _C2 are used.

As shown in FIG. 5, the switches 12 to 15 in one SC circuit 10 having a negative equivalent resistance value are CMOS switches 82 formed by connecting N-channel MOSFETs 71 to 74, respectively, and P-channel MOSFETs 75 to 78, respectively, in parallel.
It consists of 85 to 85 pieces. The signal S _S1 shown in FIG. 7 is supplied to the gates of the N-channel MOSFETs 71 and 74, and the signal S _S1 is supplied to the gates of the P-channel MOSFETs 75 and 78 via a CMOS inverter 79.
The signal S _S2 in FIG. 7 is applied to the gates of MOSFETs 72 and 73, and the above signal is applied to the gates of P-channel MOSFETs 76 and 77 via a CMOS inverter 80.
S _S2 are supplied respectively.

In such a configuration, with the DC voltage V ₁ being supplied to the other end of the CMOS switch 83 and the ground potential being supplied to the other end of the CMOS switch 85, each of the CMOS switches 82 to 85 is connected to the signals S _S1 ,
A case where switch control is performed according to S _S2 will be explained. Now, when the signal S _S2 is at a high level,
CMOS switches 83 and 84 are turned on.
At this time, the other end of the capacitor 11 (f in FIG.
A charge of −C ₁ · V ₁ is accumulated at the point ). Next, when the signal S _S1 is at a high level, the CMOS switch 82,
85 is turned on. At this time, in order to cancel the negative charge that has been accumulated in advance at the above point f,
Positive charge +C ₁ ·V ₁ flows from the ground point through the CMOS switch 85 . This kind of action is 1
Since it is repeated _S times per second, CMOS
When the direction of the current flowing through the switch 85 to the ground point is positive, the value I of the current flowing through this SC circuit is given by the following equation.

−I=C ₁・V ₁・_S ………(6) The value of the equivalent resistance R in this SC circuit is the supply voltage V ₁ divided by the above current I, so
This R is given by the following formula.

R=V ₁ /−C ₁・V ₁・_S =−1/C ₁・_S ………(7) The right side of this equation (7) is the same as the right side of the above equation (1), and Fig. 5 It can be seen that the SC circuit has a negative equivalent resistance depending on the frequency _S.

The switches 22 to 25 in the other SC circuit 20 having a positive equivalent resistance value are, as shown in FIG.
to 105. The signal S _C1 in FIG. 7 is applied to the gates of the N-channel MOSFETs 91 and 93, and the P-channel MOSFETs 95 and 97
The above-mentioned signal S _C1 is supplied to the gates of the above-mentioned N channels via the CMOS inverter 99, respectively.
The signal S _C2 shown in FIG. 7 is supplied to the gates of the MOSFETs 92 and 94, and the signal S _C2 is supplied to the gates of the P-channel MOSFETs 96 and 98 via a CMOS inverter 100, respectively.

In such a configuration, DC voltage V ₂ is now supplied to the other end of the CMOS switch 102, and the CMOS
A case will be described in which the CMOS switches 102 to 105 are controlled in accordance with the signals S _C1 and S _C2 while the other end of the switch 104 is supplied with a ground potential. When the signal S _C1 is now at a high level, the CMOS switches 102 and 104 are turned on. At this time, the capacitor 21 has C ₂ and V ₂
charge is accumulated. Next, when the signal S _C2 becomes high level, the CMOS switches 103 and 10
5 is turned on, and the charge that has been stored in the capacitor 21 is discharged to the ground point. That is, positive charges are drained from this circuit. This kind of operation is repeated _C times per second, so from the other end of the capacitor 21 (point g in Figure 6)
When the direction of the current flowing through the CMOS switch 104 to the ground point is positive, the value I of the current flowing through this SC circuit is given by the following equation.

I=C ₂・V ₂・_C ………(8) Also, the value of the equivalent resistance R in this SC circuit is
Since it is the supply voltage V ₂ divided by the current I, this R is given by the following equation.

R=V ₂ /C ₂・V ₂・_C = 1/C ₂・_C ………(9) The right side of equation (9) is the same as the right side of equation (2) above, and SC in Figure 6 It can be seen that the circuit has a positive equivalent resistance depending on the frequency _C.

FIG. 8 is a block diagram showing the structure of another embodiment of the invention. In this embodiment circuit, a frequency dividing circuit 110 is added to the embodiment circuit of FIG. This frequency dividing circuit 110 is for dividing the frequency of the oscillation output signal S _S of the Schmitt type oscillation circuit 50 by n, and the one SC circuit 10 divides the frequency of the oscillation output signal S S by n instead of the above-mentioned oscillation output signal S _S. It is controlled by S _S ′.

According to such a configuration, the frequency _S of the oscillation output signal S _S is controlled to be constant at n times that in the case of FIG. 2.

FIG. 9 is a circuit diagram showing a specific configuration of the frequency dividing circuit 110 in FIG. 8. This frequency dividing circuit 110 is an example in which the value of n is 8, that is, the frequency of the oscillation output signal S _S is divided by 8, and is a well-known circuit composed of three D-type flip-flop circuits 111 to 113. The above three flip-flop circuits 11
The data input terminals D from 1 to 113 are the respective first
They are connected in multiple stages such that the second output terminal Q in the previous stage is connected to the clock input terminal CP in the latter stage. Then, the oscillation output signal _S
is supplied to the final stage flip-flop circuit 113.
A signal S _S ' whose frequency has been divided by eight is output from the second output terminal. Incidentally, in order to change the frequency division ratio n, the number of flip-flop circuits may be increased or decreased as necessary.

FIG. 10 is a block diagram showing the configuration of still another embodiment of the present invention. In this example circuit,
A frequency dividing circuit 110 similar to the circuit of FIG. 8 and two synchronizing circuits 120A and 120B are added. For example, the frequency dividing circuit 110 waits for a configuration similar to that shown in FIG _.
The frequency is divided by 8 and the signal S _S ' is output. One of the above synchronous circuits 120A receives the signal S _S before being frequency-divided by 8,
This is for synchronizing the signal S _S ' after frequency division by 8, and the one SC circuit 10 is controlled by the output signal S _SO ' of the synchronization circuit 120A.
The other synchronization circuit 120B is for synchronizing the reference signal S _C with the oscillation output signal S _S of the Schmitt oscillation circuit 50, and is used for synchronizing the reference signal S C with the oscillation output signal S S of the Schmitt type oscillation circuit 50.
is controlled by the output signal S _CO of this synchronization circuit 120B.

Figure 11 shows the synchronous circuit 120A, 1 in Figure 10.
20B is a circuit diagram specifically showing 20B. FIG. Note that the synchronous circuits 120A and 120B have the same circuit configuration, except for the input signals. In the figure, reference numerals 121 and 122 are rise synchronized D-type flip-flop circuits, and both flip-flop circuits 121 and 12 are
The oscillation output signal S _S from the Schmitt type oscillation circuit 50 is supplied to the clock input terminal (CP) of No. 2. The data input terminal D of one of the flip-flop circuits 121 is supplied with the divided output signal S _S ' of the frequency divider circuit 110 in the case of the synchronous circuit 120A, and the signal S _C in the case of the synchronous circuit 120B. . The signal Q ₁ at the output terminal Q of one flip-flop circuit 121 is supplied to the data input terminal of the other flip-flop circuit 122 and also to the inverter 123 . The output signal ₁ of the inverter 123 is combined with the signal Q ₂ of the output terminal of the other flip-flop circuit 122.
It is fed in parallel to NOR gate 124. the above
The output signal X of the NOR gate 124 is passed through two cascade-connected inverters 125 and 126.
Provided to NAND gate 127 and NOR gate 128. The output signal of the inverter 126 is transmitted to four inverters 129 to 1 connected in cascade.
32 to the above NAND gate 127 and
Provided to NOR gate 128. Further above
The output signal of NAND gate 127 is inverter 1
33. and the inverter 133
The output signal of the flip-flop circuit 121 is
When the signal supplied to S _S ′ is
When the signal supplied to this SC circuit 10 as a signal for controlling the switches 13 and 14 in the circuit 10 and supplied to the flip-flop circuit 121 is _SC , the switch 2 in the other SC circuit 20 is
The signal is supplied to this SC circuit 20 as a signal for controlling the signals 3 and 25. When the signal supplied to the flip-flop circuit 121 is S _S ', the output signal of the NOR gate 128 is sent to this SC circuit 10 as a signal for controlling the switches 12 and 15 in the one SC circuit 10. When the signal supplied to the flip-flop circuit 121 is _SC , the switch 22 in the other SC circuit 20,
This SC circuit 2 is used as a signal to control 24.
0.

Synchronous circuit 12 configured as shown in FIG.
0A or 120B operates as follows. Assume now that, for example, the signal S _S ' has a phase shift as shown in FIG. 12 with respect to the oscillation output signal S _S from the Schmitt type oscillation circuit 50. Flip-flop circuits 121 and 122 output signals Q ₁ and 122 in synchronization with the rising edge of a clock input signal, that is, a signal S _S .
Set the level of Q ₂ to match the input signal,
Since the previous output level is maintained when the signal SC falls, both output signals Q ₁ and Q ₂ change as shown in FIG. 12. Therefore, as the output signal _X of the NOR gate 124,
A pulse signal that is at a high level for only one period of S _S is obtained. A circuit consisting of inverters 129 to 132, 133, NAND gate 127, and NOR gate 128 to which this signal
By using the delay time of 2, a two-phase signal S _S1 , whose high level periods do not overlap as shown in FIG.
A pair of signals as shown in Figure 12 corresponding to S _S2
Forms S′ _SO1 and S′ _SO2 . Moreover, the switches 12 and 15 in the SC circuit 10, which are controlled by one of the signals S' _SO1 , are kept on for approximately one cycle of the signal S _S . In other words, one of the above
The period during which the positive charge flows into the SC circuit 10 is
The period is set to approximately correspond to one cycle of the signal S _S. On the other hand _, even in the synchronization circuit 120B to which the signal _SC is supplied as an input signal, the output signal It will be done. Furthermore, from this signal X, a pair of signals corresponding to the two-phase signals S _C1 and S _C2 as shown in FIG.
S _CO1 and S _CO2 are formed. Moreover, the 12th of these
The switches 22 and 24 in the SC circuit 20 are controlled by the signal S _CO1 corresponding to the signal S' _SO1 in the figure.
It is turned on for approximately one cycle of the signal S _S . That is, the period during which positive charge flows out from the other SC circuit 20 is also set to a period corresponding to approximately one cycle of the signal S _S , as in the case of the one SC circuit 10. As a result, in the embodiment circuit of FIG. 10, the above equation (4) holds true, thereby preventing the occurrence of errors when the oscillation frequency is relatively large. Moreover, as shown in Fig. 12, the signals S' _SO1 and S' _SO2
(or S' _CO1 and S' _CO2 ) do not overlap, so switches 12, 15 and 13, 14 are not turned on at the same time in SC circuit 10, causing an error in current _I1. do not. This also applies to the SC circuit 20.

Note that this invention is not limited to the above embodiments, and various modifications are possible. For example, in the above embodiment circuit, the oscillation circuit whose oscillation frequency is adjusted according to the combined current value of the output currents of the SC circuits 10 and 20 is the Schmitt type oscillation circuit 50. The oscillation circuit may have any configuration as long as it has a function. Further, in the above embodiment circuit, a case has been described in which one SC circuit 10 having a negative equivalent resistance is controlled by the signal S _S and the other SC circuit 20 having a positive equivalent resistance is controlled by the signal S _C. These may be configured to be controlled by each other's signals.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an oscillation circuit that can stably and accurately generate a signal having a frequency that is an arbitrary multiple of a reference signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the general configuration of a speech recognition circuit, FIG. 2 is a circuit diagram showing the configuration of an embodiment of an oscillation circuit according to the present invention, and FIG. 3 is a Schmitt type circuit diagram in the circuit shown in FIG. Waveform diagram showing the operation of the oscillation circuit, No. 4
The figure is a characteristic diagram of the circuit in Figure 2, Figures 5 and 6 are circuit diagrams specifically showing the switched capacitor circuit used in the circuit in Figure 2 above, and Figure 7 is a characteristic diagram of the circuit in Figure 2. 8 is a block diagram showing another embodiment of the present invention; FIG. 9 is a circuit diagram showing a specific configuration of a part of the circuit shown in FIG. 8; FIG. 10 is a timing chart of signals used in the circuit shown in the figure. 11 is a block diagram showing a configuration of still another embodiment of the present invention, FIG. 11 is a circuit diagram showing a specific configuration of a part of the circuit of FIG. 10, and FIG. 12 is a timing chart of the circuit of FIG. 10, 20... Switched capacitor circuit (SC circuit), 11, 21... Capacitor, 30...
... Integration, 40 ... Voltage buffer circuit, 50 ... Schmitt type oscillation circuit, 110 ... Frequency division circuit, 12
0A, 120B...Synchronous circuit.

Claims (1)

[Claims] 1. A first means whose resistance value is set according to the frequency of the first signal and has a negative or positive equivalent resistance; and a first means whose resistance value is set according to the frequency of the second signal. a second means configured to have a positive or negative equivalent resistance, a third means for supplying a DC bias to the first and second means to flow a DC current, respectively; a fourth means for outputting an oscillation signal whose frequency is adjusted according to a combined current value of output currents of the means; and a fifth means for feeding back the oscillation signal as a first signal to the first means. An oscillation circuit characterized by: 2. A first means whose resistance value is set according to the frequency of the first signal and has a negative or positive equivalent resistance; and a first means whose resistance value is set according to the frequency of the second signal and has a positive or negative equivalent resistance. a second means having an equivalent resistance of; a third means for supplying a DC bias to the first and second means to flow a DC current respectively; and a combination of output currents of the first and second means. a fourth means for outputting an oscillation signal whose frequency is adjusted according to the current value;
and fifth means for feeding back the signal to the first means. 3 The first means has a resistance value set according to the frequency of the first signal and has a negative or positive equivalent resistance, and the first means has a resistance value set according to the frequency of the second signal and has a positive or negative equivalent resistance. a second means having an equivalent resistance of; a third means for supplying a DC bias to the first and second means to flow a DC current respectively; and a combination of output currents of the first and second means. a fourth means for outputting an oscillation signal whose frequency is adjusted according to the current value; a fifth means for dividing the frequency of the oscillation signal; synchronizing the frequency-divided output signal of the fifth means with the oscillation signal; a sixth means for feeding back the synchronized signal as the first signal to the first means; and a sixth means for synchronizing the second signal with the oscillation signal and supplying the synchronized signal to the second means. 7th to do
An oscillation circuit characterized by comprising the following means. 4. The oscillation circuit according to claim 1, wherein the first and second means are each constituted by a switched capacitor circuit including a capacitor and a plurality of switches. 5. A DC voltage source in which the third means supplies a constant DC voltage to one of the first and second means;
A variable direct current voltage source that supplies a direct current voltage to the other of the first and second means for adjusting the frequency of the oscillation signal output from the fourth means. Section or Section 2 or Section 3
The oscillation circuit described in section. 6. The fourth means has first and second threshold voltages, and the threshold voltage of either one is determined according to a combined current value of the output currents of the first and second means. The oscillation circuit according to claim 1, 2, or 3, which is constituted by a Schmitt-type oscillation circuit that is adjusted.