JPS60109331A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To obtain a signal of frequency which is an optional multiple of that of a reference signal from the reference signal stably with high precision by utilizing the oscillation signal of an oscillation circuit which uses a crystal oscillator, etc., as the reference signal. CONSTITUTION:A switched capacitor circuit (SC circuit) 10 has its resistance value set according to the frequency fS of an oscillation signal SS from a Schmitt type oscillation circuit 50 and also has a negative equivalent resistance. An SC circuit 20, on the other hand, has its resistance value set according to the reference signal SC having a stable frequency, i.e. frequency fC of the oscillation output signal SS of the oscillation circuit using a crystal oscillator and also has a positive equivalent resistance. An integrating circuit 30 integrates the current flowing through a point (b) to obtain a voltage V0. Its output voltage is supplied to the Schmitt type circuit 50 through a voltage buffer circuit 40. Then, the Schmitt type oscillation circuit 50 generates an osicllation output SS of desired frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a frequency-controlled oscillation circuit that generates a signal having an arbitrary multiple of a frequency from a signal having a stable frequency.

[Technical background of the invention and its problems]

Recently, devices that perform speech synthesis using digital technology have been developed and put into practical use. In this device, for example, noise or white noise is used as a sound source, and an analog audio signal is obtained by passing the signal from this sound source through a number of i-digital filter circuits.

The conditions for each of the digital filter circuits are set in accordance with the analog audio signal to be obtained at that time. Furthermore, the conditions for each digital filter circuit in the Kamiyaku digital speech synthesizer are set based on the results of analyzing and recognizing actual speech.

FIG. 1 is a circuit diagram showing a general configuration of a speech recognition circuit that performs the above-mentioned speech recognition. In FIG. 1, 1 is a microphone amplifier. This microphone amplifier 1 is for amplifying an analog signal converted by a microphone (not shown). The output of the microphone amplifier 1 is, for example, 4 ([) pantone filter circuit (BPF) 2
A, 2B.

,? C and 2D in parallel. Furthermore, the signals that have passed through 2B, 2C, and 2D are sent to the upper pantono and Sfil 1 circuit 2, and are sent to four detection circuits (DET) 3 A, 3
B.

Detected by 3C and 3D, each detection signal is 4
each low-pass filter circuit LLPF14A.

Supplied to 4B, 4C, and 4D.

4B and 4C for the above-mentioned low-pass filter circuit 4.

The signal passed through 4Df is sent to the analog/digital conversion circuit (A7'DJ(l) via multiplexer LMPX) and 5.
selectively supplied to i. The digital output from the analog/digital conversion circuit 6 becomes the recognition result for the input voice from the microphone.

By the way, in recent speech recognition circuits, switched capacitor filter technology has been used to achieve higher circuit integration and accuracy.
Microphone amplifier 1, bandpass filter circuit 2
The Hi-Noyas filter circuit 4 is entirely constructed using switched capacitor circuits. In a circuit using this switched capacitor circuit, each switched capacitor i4
with an oscillator circuit to control the oscillator circuit.

A clock generation circuit is required to generate various clock pulses from the output of this oscillation circuit. The accuracy of a switched capacitor circuit depends on the accuracy of the clock pulse used, and conventionally, this clock pulse is formed from the output of a CR oscillation circuit, for example. However, this CR oscillation circuit has poor oscillation frequency accuracy, which deteriorates the accuracy of the switched capacitor circuit itself and, by extension, the voice recognition circuit.

[Purpose of the invention]

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to utilize as a reference signal the oscillation signal of an oscillation circuit that stably oscillates using a crystal resonator or the like. The object of the present invention is to provide an oscillation circuit that can stably and accurately generate a signal having a frequency that is an arbitrary multiple from this reference signal.

[Summary of the invention]

In the oscillation circuit according to the present invention, the resistance value is set according to the oscillation output frequency of the Schmitt type oscillation circuit, and the resistance value is set according to the frequency of the negative switched capacitor circuit having a negative equivalent resistance and the reference signal. A positive switched capacitor circuit having a positive equivalent resistance is provided, a constant DC voltage is supplied to one end of the negative switched capacitor circuit, and the positive switched capacitor circuit has a positive equivalent resistance. One end of the capacitor circuit is supplied with iIj and a current voltage having a value corresponding to the frequency of the oscillation signal to be obtained, and the high level side of the Schmitt type oscillation circuit is supplied to one end of the capacitor circuit in accordance with the combined current value of the output currents of both switched capacitor circuits. The threshold voltage is set, and the frequency of the oscillation signal of the Schmitt type oscillation circuit is adjusted accordingly.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings. FIG. 2 is a circuit diagram showing the configuration of a practical example of the oscillation circuit of the present invention. In the figure, reference numeral 10 has a capacitor and four switches 12 to 15, the resistance value of which is set according to the frequency f6 of an oscillation signal S8 from a Schmidt type oscillation circuit, which will be described later. This is a switched capacitor circuit (hereinafter abbreviated as SC circuit) having a resistance. One end of each of switches 12 and 13 is connected to one end of canister 11 in SC circuit 10, and the other end of switch 12 is connected to a ground point. One end of each of switches 14 and 15 is connected to the other end of the canister 1, and the other end of the switch 14 is connected to a ground point. and the above four switches 12
2 to 15 switches 12.1 each
5 and 13.14 are alternately turned on in response to signal S8.

20 is a capacitor 21 and four switches 22 to 25
It is an SC circuit which has a reference signal Sc with a stable frequency, for example, an oscillation output signal S of an oscillation circuit using a crystal resonator, and whose resistance value is set according to the frequency fc of the oscillation output signal S, and which has a positive equivalent resistance. . One end of each of switches 22 and 23 is connected to one end of the top and bottom 2 in this SC circuit 20, and the other end of the switch 23 is connected to a ground point. One end of each of switches 24 and 25 is connected to the other end of the canopy 21, and the other end of the switch 25 is connected to a ground point. Of the four switches 22 to 25, two switches 22, 24 and ;ts, ;ts are alternately turned on in response to the signal Sc.

The positive electrode side of the DC power source vl is connected to the 81 point to which the other end of the switch 13 in the one SC circuit 10 is connected. The positive terminal side of the variable DC power supply V is connected to the 82 points to which the other end of the switch 22 in the other SC circuit 20 is connected. The negative terminal sides of the DC power supply Vl and the variable DC power supply (2) 8 are both connected to a ground point.

Further, the other end of the switch 15 in one SC circuit 10 is connected to the other end of the switch 24 in the other SC circuit 20, and the input end of the integrating circuit 30 is connected to this connection point. . This integrating circuit 30 has a current t flowing at the above point.
- This is for integrating to obtain a voltage vo having a value and polarity corresponding to the value and polarity of this current.

The integrating circuit 30 includes a differential amplifier circuit 31 having an inverting input terminal, a non-inverting input terminal, and an output terminal, and a capacitor 3.
2, and the capacitor 32 is a differential amplifier circuit 31.
The differential amplifier circuit 3 is connected between its inverting input terminal and its output terminal, and its non-inverting input terminal is connected to the ground point.

The output voltage vo of this integrating circuit 30 is the voltage buffer circuit 4
0 to the Schmidt type oscillation circuit 50. The voltage buffer circuit 40 is composed of a differential amplifier circuit 41 having an inverting input terminal, a non-inverting input terminal, and an output terminal, the inverting input terminal and the output terminal are connected, and the voltage vo is input to the non-inverting input terminal. has been done.

The Schmitt type oscillator circuit 50 includes a non-inverting input terminal 1.
Differential amplifier circuit 51 having an inverting input terminal and an output terminal
is provided. A high-level threshold voltage vH and a low-level threshold voltage vL are alternately input to the non-inverting input terminal of the differential amplifier circuit 51. The threshold voltage V on the high level side is determined by the series connection point C of two resistors 52 and 53 connected in series between the positive polarity power supply voltage vDD application point and the output terminal of the voltage buffer circuit 40. KLj is applied to the P-channel MO8FET 54 and the N-channel MO8FET 5.
The signal is inputted to the non-inverting input terminal of the differential amplifier circuit 51 through a CMOS switch 56 consisting of 5. The threshold voltage vL on the low level side is the power supply voltage v
This voltage vL is obtained at the series connection point d of two resistors 57 and 58 connected in series between the DD application point and the negative polarity power supply voltage VSII application point.
and a CMO consisting of 6 o N-channel MO8FETs
The signal is input to the non-inverting input terminal of the differential amplifier circuit 5 via the S switch 6. Two inverters 62 and 63 are connected in series to the output terminal of the differential amplifier circuit 5, and a resistor 64 and a capacitor 65 are connected in series between the output terminal of the inverter 63 in the latter stage and the VSS application point. ing.

The output signal of the inverter 63 at the latter stage is inputted in parallel to the dart of the N-channel MO8FET 55 constituting the CMOS switch 56 and the dart of the P-channel MO8FET s y constituting the CMOS switch 61, and is input to the two inverters 66 and 67. is also entered.

The output signal of the inverter 66 is transmitted to the CMO8 switch 56.
Dart of P channel MO8FET 54 which constitutes and N channel MO8F which constitutes CMOS switch 61
f-) of ET 60 in parallel. Also,
The voltage at the series connection point e between the resistor 64 and the capacitor 65 is input to the inverting input terminal of the differential amplifier circuit 51.

The output signal of the inverter 67 is supplied to other circuits as the oscillation output signal S8 of this oscillation circuit, and this signal S8 is fed back to the one SCC circuit.

Moreover, the three differential amplifier circuits 31, 41, and 51 provided in this embodiment circuit are arranged between a positive polarity power supply voltage vDD and a negative polarity power supply voltage vI]B whose absolute value is equal to this vDD. The potential of the ground point is set to Ov, which is the intermediate potential between the threshold voltage vDD and Vli8.

In the circuit having the above configuration, the operation of the Schmi-G type oscillation circuit 50 will be explained first.

Now, the resistance ratio of the resistors 52 and 53 and the output voltage V from the voltage buffer circuit 40 are determined in advance. The threshold voltage VH obtained at point 0 is fixed according to Suppose that Now, when the output signal of the differential amplifier circuit 51 is at a high level (vDD level), the output signal of the inverter 63 is also set at a high level. It is charged with a time constant τ corresponding to the value of 65. Therefore, the voltage at point e gradually increases. On the other hand, when the output signal of the inverter 63 is at a high level, the CMOS switch 56 is turned on, and the high level side The threshold voltage vH of is input. Therefore, the differential amplifier circuit 51 compares this threshold voltage vH with the voltage at the point e.

When the voltage at point e reaches the threshold voltage vH, the output signal of the differential amplifier circuit 51 is inverted from high level to low level (Vss level). After this level inversion, the output signal of the inverter 63 is also inverted to a low level, so the capacitor 65, which has been charged up to now, is now discharged toward the VSS level via the resistor 64 with a time constant τ. Therefore, the voltage at point e now gradually decreases. On the other hand, when the output signal of the inverter 63 is at a low level, the CMOS switch 6 is turned on.
A low-level threshold voltage vL is input to the non-inverting input terminal of the differential amplifier circuit 51 via this CMOS switch 61. Therefore, at this time, the differential amplifier circuit 51 compares this threshold voltage vL with the voltage at the point e. When the falling voltage at point e reaches the threshold voltage vL, the output signal of the differential amplifier circuit 51 is inverted from low level to high level again. Similarly, the differential amplifier circuit 5 alternately compares the voltage at point e with the two threshold voltages V□, vL, so that the output signal of the inverter 63 changes between high and low levels at a predetermined period. This becomes an oscillation signal that repeats alternately. Also, inverter 67
Since the output signal S8 is the inverted signal of the inverter 63, this signal S also becomes an oscillation signal. The frequency f of the oscillation signal Ss of this Seamit type oscillation circuit 5o is
When the threshold voltages vH and vL are set constant, sb is constant, and its value is determined by the threshold voltages vH and vL, and the Luschmitt width (lVHI+IVLl
) and the time constant τ determined by the values of the resistor 64 and capacitor 65. FIG. 3 is a waveform diagram showing the relationship between the voltage ve at the point e and the output signal Ss of the inverter 63.

On the other hand, the oscillation signal S from the Seamit type oscillation circuit 5o
The equivalent resistance value R, of the SC circuit 10 to which , is input is,
Letting the value k Cl of the capacitor 11 be given by the following equation.

Similarly, the equivalent resistance value R2 of the SC circuit 20 to which the signal Sc is input is given by the following equation, assuming that the value of the capacitor 21 is C2.

Now, a positive polarity voltage is supplied from the DC power supply v1 or the variable DC power supply v2 to each one end of the SC circuit lO12θ, that is, the other end of the switch 13 in the SC circuit 10 and the other end of the switch 22 in the SC circuit 20. Therefore, direct current flows through both SC circuits 10 and 20, respectively.

Since one SC circuit 10 has a negative equivalent resistance value R1,
The direction of the current 11 flowing through the SC circuit 10 is to the left in FIG. 2 (this is taken as the direction of negative polarity).

Since the other SC circuit 20 has a positive equivalent resistance value Rt't-, the direction of the current I2 flowing through this SC circuit 20 is the second one.
The direction is to the right in the figure (this is the direction of positive polarity). That is, the directions of the currents ``InI3'' are opposite to each other. Then, a composite current of both currents ``1*lff1'' is supplied to the integrating circuit 3o.If this composite current is of negative polarity, that is, the current 1 , is larger than I2, the output voltage vo of the integrating circuit 30 gradually increases toward the positive power supply voltage VDD.Contrary to the above, when the current 11
+ ``When the combined current of 2 has positive polarity, that is, when I2 is larger than current 11, the output voltage vo of the integrating circuit 3o gradually increases toward the power supply voltage VI]B of negative polarity. Then, the output voltage vo of the integrating circuit 3o
SC circuit 10.20 while rising or falling
The output current 'InI! is in an equilibrium state, and when the combined current becomes 0, the change in the output voltage vo stops at that point, and vo does not change thereafter.

Now, let's say DC power supply V! Is it possible that the value of the variable DC power supply v2 is set equal to the value of the variable DC power supply v2? It is assumed that the f-directions C1mC2 of the shutters 11 and 21 are set equal to each other. At this time, the SC circuit O,
20, the frequencies fs, f of the two signals Ss, Sc
When c match, the combined current of currents II and I2 becomes 0.
, and the output voltage vo of the integrating circuit 30 is fixed at a certain value.

When the value of Vo is fixed, the high-level threshold voltage 8 formed in the Schmitt type oscillation circuit 50 is also fixed, and thereby the Schmitt width (Ivnl+lvt,
Since I) is also fixed, the frequency f8 of the oscillation signal S8 is also fixed.

Suppose that fs decreases from the state where the frequencies fs and fc match. When the frequency fB decreases, the above (1)
The absolute value of the SCC circuit 10 flow II given by the formula becomes small. Then, the combined current of I and I2 becomes a positive value, and the output voltage vo of the integrating circuit 30 drops toward VaS. The voltage v obtained at the 0 point in the Seamit type oscillation circuit 50 as the voltage o drops toward v88
H decreases and Schmidt width (lvu l+lVL I
) becomes narrower than before, so the frequency f8 of the oscillation output signal S8 in the Schmidt type oscillation circuit 50 increases. As the frequency f8 increases, the equivalent resistance value R1 of the SC circuit 10 becomes smaller and the absolute value of the current 1 gradually increases. Then, the combined current value of currents 1 and I2 decreases from the positive polarity toward the value of O, and becomes 0 when I8 matches f.

Therefore, f. falls, the output voltage Vo of the integrating circuit 30 increases toward DD until it matches fc,
When Vo returns to its original value, its rise stops, and when the frequency fs of the oscillation output signal Ss matches fc, f. will also stop rising.

Assume that I8 increases from the state where the frequencies fs and fC match. As the frequency fB increases, the equivalent resistance value R1 of the SC circuit 10 given by equation (1) becomes smaller than before, and the absolute value of the current 11 increases. Then, the electric current■! The combined current of I2 and I2 has a negative polarity, and the output voltage vo of the integrating circuit 30 increases toward vDD. When the voltage vo increases, the threshold voltage vII on the high level side becomes higher than before, and the Schmitt width (Iv'
Since n l+IvLl ) becomes wider than before, the frequency f8 of the oscillation output signal SR in the Seamit type oscillation circuit 5o decreases. As the frequency f decreases, the equivalent resistance value R1 of the SC circuit 1o increases, and the absolute value of the current 1 gradually decreases.

Then electrician! The combined current value of I2 and I2 increases from negative polarity toward the value of O, and becomes O when fIl matches fc.

L/ Therefore, when fB increases, the output voltage V of the integrating circuit 3o increases until it matches fc.

falls toward V118, and stops dropping when Vo reaches its original value, and when the frequency f of the oscillation output signal s8 matches fc, the falling of fs also stops.

That is, in this embodiment circuit, the DC power supply V! and the variable DC power supply vzO value are set equal, and the values of the capacitors 11.21 in the SC circuit 10.20 are set equal to each other, the oscillation output signal st1
The frequency f, is controlled to match the frequency*number fc of the signal Sc.

Next, the case of changing the setting of the variable DC power supply V will be explained. First, when v-value is set higher than vl, since the still image resistance value R2 of the SC circuit 20 is constant, the output current I of the SC circuit 20.

But it's getting bigger than before. At this time, in order to balance the currents I and 12 and make the value of the combined current 12 O, the absolute value of the output current Il of one SC circuit 10 needs to be larger than before.

By increasing the current (2), the integrator circuit 30
The output voltage vo of drops toward V8B, and then the frequency f of the oscillation output signal S8 of the Schmidt type oscillation circuit 50,
will rise. This increase in frequency fa continues until the absolute value of the output current I of the SC circuit 10 matches the absolute value of I2. That is, when vlf: is set higher than vl, the frequency 18 of the oscillation output signal Ss is controlled to be constant at a higher point than fc.

Next, if v2 is set lower than vl, the SC circuit 20
The output current 11 of is now smaller than before. At this time, in order to balance the currents Il and I2 and make the value of their combined current O, contrary to the above, the absolute value of the output current 11 of one SC circuit io must become smaller than before. be.

When the current I2 becomes smaller, the output voltage vo of the integrating circuit 30 increases toward VDD, and thereafter the frequency f8 of the oscillation output signal S8 of the Schmitt type oscillation circuit 500 decreases. This decrease in frequency fs is caused by the SC circuit 10
This continues until the absolute value of the output current I□ matches the absolute value of I2.

In other words, if v2 is set lower than vl,
The frequency fs of the oscillation output signal Ss is controlled to be constant at a point lower than fc.

By the way, in this example circuit, the oscillation frequency af [l
The condition for stabilizing is that the combined current value of the output currents F#'2 of the two SC circuits 10°2θ becomes O. That is, this stability condition is expressed by the following equation (3) By substituting the relationship of the resistance value R1*Ri given by the above equations (1) and (2) into the above equation (3), the following equation is obtained.

Cx"f8'Vt10g"j(H・Vz"0 --44
) Next, when the above equation (4) is summarized for I8, the following equation is obtained.

Since we have previously assumed that (l=('),
I8 is fc multiplied by 72771. Therefore, f by adjusting the value of the variable DC power supply v2. It is possible to create a signal SIl with a frequency afs that is an arbitrary multiple of .

FIG. 4 shows a characteristic diagram of the above embodiment circuit when C1202 is used, and the horizontal axis shows the frequency 1 of the oscillation signal S8.
8, I#:I! dJKl-J, variable DC 'ME source V
Each takes a value of 2. As shown in the figure, I8 is ■
There is a linear relationship with 2.

Here, the equivalent resistance value R in the two SC circuits 10.20
As shown in formulas (1) and (2) above, 1z RM is
If the value of cta'ct is constant, it is determined only by the frequencies fB and fc, and the value CI of the canopies 11 and 21
# Since C11 can be set with much higher precision than resistors, etc., the frequency fBafc is converted to resistors R1a and R2 with high precision. This resistance "1 a R
The difference in the values of
8 can be adjusted stably and with high precision.

Furthermore, in the above explanation, the oscillation frequency f is adjusted by changing the value of the variable DC power supply 2, but as is clear from the above equation (4), this is done by changing the value of the two S
Value C15 of capacitor 11.21 in C circuit 10.20
C! By changing the settings, you can adjust the frequency to a multiple according to the ratio. For example, by setting the values of Cano and Shita 11 and 21 so as to satisfy the relationship n"cl":C2, it is possible to HM the frequency of f8 to be n times fc. Moreover, the value of this n is equal to the variable DC power supply v2
The same applies when changing , but it is not limited to integers, but can be set to real numbers including decimals. Also, instead of (2), Vl may be configured with a variable DC power supply.

FIGS. 5 and 6 are circuit diagrams specifically showing two SC circuits 10 and 20 used in the circuit of the embodiment. In FIGS. 5 and 6, parts corresponding to those in FIG. 2 are designated by the same reference numerals. Furthermore, the signals s8' and sc are actually two-phase signals ss1. ss2 or sc4. sc
2 is used.

One of the SCC circuits 12 to 15 having a negative equivalent resistance value is an N-channel M
O8FET y J to 74 each and P channel M
It is composed of CMOS switches 82 to 85 each having O8FETs 75 to 78 connected in parallel. And the above N-channel MO8FET 7 J, 7
4, the signal S81 in FIG. 7 is connected to the P channel M.
The signal ss1 is supplied to the darts of O8FETs 75 and 78 via a CMOS inverter 79, respectively.
The signal ss2 in FIG.
, 77 no? ”-) is a CMOS inverter 80f.
The above-mentioned signal s82 is supplied through the respective terminals.

In such a configuration, with the DC voltage v1 being supplied to the other end of the CMOS switch 83 and the ground potential being supplied to the other end of the CMOS switch 85, each of the CMOS switches 82 to 85 is connected to the signal Ss1°S[+2. A case will be explained in which the switch is controlled accordingly. Now signal S82
When K is at a high level, the CMOS switches 83 and 84 are turned on.

At this time, a charge of -clevl is accumulated at the other end of the armpit 1) (point f in FIG. 5). Next, signal S81
When is at a high level, iiCMOS switch 82,85 is turned on. At this time, CMO is connected from the ground point to cancel the negative charge that has been accumulated in advance at the point f.
A positive charge +C1 mV is supplied via the S switch 85. Since this operation is repeated fs times for 10 seconds, the CMO8 switch 85f! : When the direction of the current flowing through the ground AK is positive, the value of the current flowing through this SC circuit is given by the following equation.

- to C1.Vl.fB...Concave (6) Since the value of the equivalent resistance R in this SC circuit is divided by the supply voltage Vl and the above current, R is given by the following equation.

The right side of equation (7) is the same as the right side of equation (1) above, and it can be seen that the SC circuit in FIG. 5 is a circuit having a negative equivalent resistance depending on the frequency f8.

The switches 22 to 25 in the other SC circuit 2o having a positive equivalent resistance value are N-channel M as shown in FIG.
O8FET 91 to 94 each and P channel MO
It is composed of CMOS switches LO2 to 105 each having 8FETs 95 to 98 connected in parallel. And the above N-channel MO8FETs 91 and 93
The signal SC1 in FIG. 7 is connected to the P channel MO
The signal Sc1 is supplied to the darts of the 3FETs 95 and 97 through a CMOS inverter 99, and the signal So2 in FIG. 7 is supplied to the darts of the N-channel MO3FETs 92 and 94,
The signal Sc2 is supplied to darts 6 and 98 via a CMOS inverter 100, respectively.

In such a configuration, the CMOS switch 102
0 and supplies DC voltage v2 to the other end of the CMOS switch 10.
A signal S is applied to each CMOS switch 1θ2 to 105 while supplying a ground potential to the other end of 4. +r A case where the switch is controlled according to h2 will be explained. When the signal Sc1 is high and the signal is high, the CMOS switch 102,
104 is turned on. At this time, Canogu shift 2
1 accumulates a charge of C,=V. Next, the signal Sc
2 becomes high level, this time CMOS switch 103
．． 105 is turned on, and the charge that has been stored in the capacitor 21 is discharged to the ground point.

This kind of operation is repeated pfc times per second, so
When the direction of the current flowing from the other end of the capacitor 2 (point g in FIG. 6) to the ground point via the CMOS switch 104 is positive, the value of the current flowing through this SC circuit is given by the following equation.

X=C, *V2・fc... (δ) Also, the value of the equivalent resistance R in this SC circuit is the supply voltage V2 divided by the above current I, so R is given by the following formula .

The right-hand side of this equation (9) is the same as the right-hand side of equation (2) above, and hD
, it can be seen that the SC circuit in FIG. 86 is a circuit having a positive equivalent resistance depending on the frequency fc.

Note that this invention is not limited to the above embodiments, and various modifications are possible. For example, in the above embodiment circuit, the oscillation circuit whose oscillation frequency is adjusted according to the combined current value of the output currents of the SC circuit 10.20 is the Seamit type oscillation circuit 5Q, but this is not the case. Any configuration may be used as long as the oscillation circuit has a function. Further, in the above embodiment circuit, a case has been described in which one SC circuit 10 having a negative equivalent resistance is controlled by the signal SI1, and the other SC circuit 20f having a positive equivalent resistance is controlled by the signal Sc. It may be configured to be controlled by the other signal.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an oscillation circuit that can stably and accurately generate a signal having a frequency that is an arbitrary multiple of a reference signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the general configuration of a speech recognition circuit, FIG. 2 is a circuit diagram showing the configuration of an embodiment of an oscillation circuit according to the present invention, and FIG. 3 is a Schmidt type circuit in the circuit shown in FIG. A waveform diagram showing the operation of the oscillation circuit, FIG. 4 is a characteristic diagram of the circuit shown in FIG. 2, and FIGS. 5 and 6 are circuit diagrams specifically showing the switched capacitor circuit used in the circuit shown in FIG. 2, respectively. FIG. 7 is a timing chart of signals used in the circuits of FIGS. 5 and 6. 10.20...Switched capacitor circuit (sc times f
lr), 11.21... Capacitor, 3o... Integrating circuit, 40... Voltage buffer circuit, 5o... Schmitt type oscillation circuit, 31, 41.51... Differential amplifier circuit. Applicant's agent Patent attorney Takehiko Suzue No. 3 [Figure 4 fc +s Figure 5

Claims (4)

[Claims] (1) A first means whose resistance value is set according to the frequency of the first signal and has a negative or positive equivalent resistance; or a second means having a negative equivalent resistance, and the first I.
a third means for supplying a DC bias to the second means to cause a DC current to flow respectively; a fourth means for fully outputting an oscillation signal whose frequency is adjusted according to the combined current value of the output currents of the second means; and a fifth means for feeding back the oscillation signal as a first signal to the first means. An oscillation circuit characterized by comprising means. (2) Case 1 above. The second means is a capacitor and a compound e.
(7) The oscillation circuit according to claim 1, each comprising a switched capacitor circuit including a switch. (3) The third means is the first means. a DC voltage source supplying a constant DC voltage to one of the second means;
．． Claim 1, further comprising a variable DC voltage source that supplies the other of the second means with a DC voltage for adjusting the frequency of the oscillation signal output from the fourth means. Oscillation circuit. (4) The fourth means is the first means. a second threshold voltage, one of which has a second threshold voltage; Second
Claim 1 comprising a Schmitt type oscillation circuit that is adjusted according to the combined current value of the output currents of the means.
The oscillation circuit described in section.