JPS60109332A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To obtain a signal of frequency which is an optional multiple of that of a reference signal from the reference signal stably with high precision by utilizing the oscillation signal of an oscillation circuit which has a stable frequency and uses a crystal oscillator, etc., as the reference signal, and feeding the oscillation signal back after frequency division. CONSTITUTION:A switched capacitor circuit (SC circuit) 10 has its resistance value set according to the frequency fS of an oscillation signal SS and also has a negative equivalent resistance. An SC circuit 20, on the other hand, has its resistance value set according to the frequency fC of the oscillation output signal SS of the frequency-stabilized oscillation circuit using a crystal oscillator and also has a positive equivalent resistance. An integrating circuit 30 integrates the current flowing through a point (b) to obtain a voltae V0. Its output voltage is supplied to the Schmitt type oscillation circuit 50 through a voltage buffer circuit 40. The output SS of the oscillation circuit 50 is an oscillation output of desired frequency, but part of the output of the oscillation circuit 50 is frequency-divided by (n) through a frequency dividing circuit 110 and fed back to the SC circuit 10. Thus, an (n)-fold output is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a frequency-controlled oscillation circuit that generates a signal having an arbitrary multiple of a frequency from a signal having a stable frequency.

[Technical background of the invention and its problems]

Recently, devices that perform speech synthesis using digital technology have been developed and put into practical use. In this device, for example, an impulse or white noise is used as a sound source, and the signal from this sound source is passed through several digital filter circuits to obtain an analog audio signal.

The conditions for each of the digital filter circuits are set in accordance with the analog audio signal to be obtained at that time. Furthermore, the conditions for each digital filter circuit in the digital speech synthesizer are set based on the results of analyzing and recognizing actual speech.

FIG. 1 is a circuit diagram showing a general configuration of a speech recognition circuit that performs the above-mentioned speech recognition. In FIG. 1, 1 is a microphone amplifier. This microphone amplifier 1 is used to amplify an analog signal converted by a microphone (not shown). The output of the microphone amplifier 1 is sent to, for example, four band-pass filter circuits (BPF) 2;
It is supplied to B, 2C, and 2D in parallel.

Furthermore, the band pass filter circuits 2A and 2B.

The signal passing through 2C and 2D is sent to 4 detection circuits (DET)
,? A, 3B, 3C, and 3D are detected, and each detection signal is sent to each of the four low-pass filter circuits (LP
F) 4A, 4B, 4C.

Supplied to 4D. In the low-pass filter circuit 4, 4
The signals that have passed through B, 4C, and 4D are sent to a multiplexer (MP
X) Analog/digital conversion circuit (A/D
)6. The digital output from the analog/digital conversion circuit 6 becomes the recognition result for the input voice from the microphone.

By the way, recent speech recognition circuits have become highly integrated and highly accurate by using switched capacitor filter technology.
The microphone amplifier 1, the bandpass filter circuit 2, and the bandpass filter circuit 4 are all constructed using switched capacitor circuits. A circuit using this switched capacitor circuit requires an oscillation circuit and a clock generation circuit for generating various clock pulses from the output of the oscillation circuit in order to control each switched capacitor circuit. The accuracy in switched capacitor circuits depends on the accuracy of the clock pulses used. Conventional clock pulses are, for example, those formed from the output of a CR oscillation circuit. However, this CR oscillation circuit has poor oscillation frequency accuracy, which deteriorates the accuracy of the switched capacitor circuit itself and, by extension, the voice recognition circuit.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to utilize the oscillation signal of an oscillation circuit that stably oscillates using a crystal resonator etc. as a reference signal. The object of the present invention is to provide an oscillation circuit that can stably and accurately generate a signal having a frequency that is an arbitrary multiple from this reference signal.

[Summary of the invention]

In the oscillation circuit according to the above, the resistance value is set according to the oscillation output frequency of the Seamit type oscillation circuit, and the resistance value is set according to the oscillation output frequency of the Seamit type oscillation circuit. The resistance value is set according to the frequency of the shifter circuit and the reference signal.
A positive switched capacitor circuit having a positive equivalent resistance is provided, a constant DC voltage is supplied to one end of the negative switched capacitor circuit, and a constant DC voltage is supplied to one end of the negative switched capacitor circuit. A DC voltage having a value corresponding to the frequency of the oscillation signal to be obtained is supplied to one end, and the threshold voltage on the high level side of the Schmitt type oscillator circuit is determined according to the combined current value of the output currents of the two switched capacitor circuits. settings are made, and the frequency of the oscillation signal of the Schmitt type oscillation circuit is adjusted accordingly.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings. FIG. 2 is a circuit diagram showing the configuration of an embodiment of the oscillation circuit of the present invention. In the figure, 10 has a capacitor 1 and four switches 12 to 15, the resistance value of which is set according to the frequency ft3 of an oscillation signal Ss from a Schmitt type oscillation circuit, which will be described later, and which has a negative equivalent resistance. This is a switched capacitor i4 circuit (hereinafter abbreviated as 80 circuit). One end of a capacitor 11 in this SC circuit 10 is connected to one end of each of switches 12 and 13, and the other end of the switch 12 is connected to a ground point. One end of each of switches 14 and 15 is connected to the other end of the capacitor 11, and the other end of the switch 14 is connected to a ground point. And two switches 12 and 15 each of the four switches 12 to 15 mentioned above.
and 13, 14 are alternately turned on in response to the signal Ss.

20 is a capacitor 21 and four switches 22 to 25
An SC circuit having a stable frequency, a resistance value set according to the frequency f of an oscillation output signal Sc of an oscillation circuit using a crystal resonator, and a positive equivalent resistance. is. One end of each of switches 22 and 23 is connected to one end of capacitor 2 in SC circuit 20, and the other end of switch 23 is connected to a ground point. The other end of the capacitor 21 is connected to one end of each of switches 24 and 25, and the other end of the switch 25 is connected to a ground point. And two of the four switches 22 to 25, respectively.
The individual switches 22.24 and 23.25 are alternately turned on in response to the signal Sc.

The positive electrode side of the DC power supply V□ is connected to the 81 point to which the other end of the switch 13 in the one SC circuit 10 is connected. The positive terminal side of the variable DC power supply (2) is connected to the 82 points to which the other end of the switch 22 in the other SC circuit 20 is connected.

The negative pole sides of the DC power supply V1 and the variable DC power supply V2 are both connected to a ground point. Also, one of the above SCs
The other end of the switch 15 in the circuit 10 and the other SC circuit 20
The other end of the switch 24 is connected to the other end of the switch 24, and the input end of the integrating circuit 30 is connected to this connection point. This integrating circuit 30 is for integrating the current flowing at the above-mentioned points to obtain a voltage (2o) having a value and polarity corresponding to the value and polarity of this current.

The integrating circuit 30 includes a differential amplifier circuit 31 having an inverting input terminal, a non-inverting input terminal, and an output terminal, and a capacitor 3.
2, and the canopy arm 32 is a differential amplifier circuit 3.
The differential amplifier circuit 31 is connected between its inverting input terminal and its output terminal, and its non-inverting input terminal is connected to a ground point.

The output voltage V of this integrating circuit 30. is voltage buffer circuit 4
0 to the Schmidt type oscillation circuit 50. The voltage buffer circuit 40 is composed of a differential amplifier circuit 41 having an inverting input terminal, a non-inverting input terminal, and an output terminal, and the inverting input terminal and the output terminal are connected, and the non-inverting input terminal receives the voltage (2). is entered.

The Schmitt type oscillator circuit 50 includes a non-inverting input terminal,
Differential amplifier circuit 51 having an inverting input terminal and an output terminal
is provided. The non-inverting input terminal of this differential amplifier circuit 51 is connected to the high-level side threshold value LV8 and υ section No.4.
7/jEII Gm maximum value voltage ■1 is inputted alternately. Threshold voltage v on the high level side above
8 is a positive polarity voltage vDD application point and the voltage 79
This voltage v is obtained at the series connection point C of two resistors 52 and 53 connected in series between the output terminal of the 771 circuit 40
H is P channel MO8FET 54 and N channel M
The signal is input to the non-inverting input terminal of the differential amplifier circuit 51 via a CMOS switch 56 consisting of an O8FET 55. The threshold voltage vL on the low level side is
This voltage vL is obtained at the series connection point d of two resistors 57 and 58 connected in series between the power supply voltage vDD application point and the negative polarity power supply voltage vs8 application point.
The signal is input to the non-inverting input terminal of the differential amplifier circuit 51 via a CMOS switch 61 consisting of an FET 59 and an N-channel MO8FET 6o. Two inverters 62 . are connected to the output terminals of the differential amplifier circuit 51 .
63 are connected in series, and a resistor 64 and a capacitor 65 are connected in series between the output end of the inverter 63 at the subsequent stage and the vss application point.

The output signal of the inverter 63 at the latter stage is input in parallel to the dart of the N-channel MO8FET 55 that constitutes the CMOS switch 56 and the dart of the P-channel MO8FET 59 that constitutes the CMOS switch 61, and is input to the two inverters 66. It is also entered in .67. The output signal of the inverter 66 is connected to the dirt of the P-channel MO8FET 54 which constitutes the CMO3 switch 56 and the N-channel MO8FET which constitutes the CMO8 switch 6.
It is input to the gate of O8FET 60 in parallel. Further, the voltage at the series connection point e between the resistor 64 and the capacitor 65 is input to the inverting input terminal of the differential amplifier circuit 5. The output signal of the inverter 67 is supplied to other circuits as the oscillation output signal Sl of this oscillation circuit, and this signal Ss is fed back to the one SC circuit 10.

In addition, the three differential amplifier circuits 31, 41, and 51 provided in this embodiment circuit are configured to operate between a positive polarity power supply voltage vDD and a negative polarity power supply voltage ■8B whose absolute value is equal to this vDD. Since it is now operated by voltage, the potential of the ground point is O, which is the intermediate potential between the two military pressures DD and vss.
It is set to V.

In the circuit having the above configuration, the operation of the Schmitt type oscillation circuit 50 will be explained first. Now, in advance, resistors 52 and 5
3 and the output voltage V from the voltage buffer circuit 40.

The threshold voltage vH obtained at point 0 is fixed according to 9, and this voltage vH becomes higher than the threshold voltage vL obtained at point d according to the resistance ratio of the resistor 57.58. Suppose that When the output signal of the differential amplifier circuit 51 is now at a high level (DD level), the inverter 6
Since the output signal of 3 is also made high level, the capacitor 65
is connected to the resistor 64 and the canister 65 via the resistor 64.
It is charged with a time constant τ depending on the value of . Therefore, the voltage at point e gradually increases. On the other hand, when the output signal of the inverter 63 is at a high level, the CMOS switch 56 is turned on, and the high level side signal is connected to the non-inverting input terminal of the differential amplifier circuit 51 via this CMOS switch 56. A threshold voltage vH is input. Therefore, the differential amplifier circuit 5 compares this threshold voltage vH with the voltage at the point e. Then, when the voltage at point e reaches the threshold voltage (■□), the output of the differential amplifier circuit 51 (i. , inverter 63
Since the output signal of
It is discharged toward the sS level with a time constant τ. Therefore, the voltage at point e now gradually decreases. On the other hand, when the output signal of the inverter 63 is at a low level, C
The MOS switch 61 is turned on, and the differential amplifier circuit 5
A low-level threshold voltage VL is inputted to the non-inverting input terminal of No. 1 through this CMOS switch 6. Therefore, at this time, the differential amplifier circuit 5 compares this threshold voltage VL with the voltage at the point e. When the falling voltage at point e reaches the threshold voltage (1), the output signal of the differential amplifier circuit 51 is inverted from the low level to the high level again. Similarly, the differential amplifier circuit 51 calculates the voltage at point e and the two threshold voltages v1□, VI.

By alternately comparing the output signal of the inverter 63, the output signal of the inverter 63 becomes an oscillation signal that alternately repeats high level and low level at a predetermined period. Furthermore, since the output signals S, I of the inverter 67 are the inverted signals of the inverter 63,
This signal Ss also becomes an oscillation signal. The frequency f of the oscillation signal SB of this Schmitt type oscillator circuit 50 is constant when the threshold voltages vH and vL are set constant, and its value is determined by the threshold voltages vH and VL. The time constant τ is determined based on the determined Schmitt width (1VH1+1VL1) and the values of the resistor 64 and capacitor 65. FIG. 3 is a waveform diagram showing the relationship between the voltage v8 at the 0 point and the output signal of the inverter 63.

On the other hand, the oscillation signal S from the Schmidt type oscillation circuit 50
The equivalent resistance value R1 of the SC circuit 10 to which s is input is:
Letting C1 be the value of Cano 4 Cita 11, it is given by the following equation.

R□=-□・・・・・・(1) C1・I8 Similarly, signal S. The 1-equivalent resistance value R2 of the SC circuit 2° to which is inputted is given by the following equation, assuming that the value of the capacitor 21 is 02.

R,=□・・・・・・(2) C2・fc Now, one end of each of the above SC circuits 10 and 20, that is, the other end of the switch 13 in the SC circuit 10 and the other end of the switch 22 in the SC circuit 20. Since positive polarity voltage is supplied from DC power supply V or variable DC power supply ■2, both S
Direct current flows through each of the C circuits 10 and 20. Since one SC circuit 10 has a negative equivalent resistance value R1, the direction of the electric current 1 flowing through the two SC circuits 10 is to the left in FIG. 2 (this is taken as the direction of negative polarity). Since the other SC circuit 20 has a positive equivalent resistance value R2, this SC circuit 2
The direction of the current 2 flowing through the current 0 is the right direction in FIG. 2 (this is the direction of positive polarity). That is, the above current I,
The directions of I and I are opposite to each other. and integrating circuit 3o
Both currents are 1111! A composite current of now,
If this combined current has negative polarity, that is, the current ■□ is I
2. The output voltage V of the integrating circuit 30 when the voltage is also large. increases sequentially toward the positive power supply voltage vDD. Contrary to the above, electric current engineer □.

When the composite current of ■ is positive, that is, when the current I□ is larger than the current I2, the integrating circuit 30
The output voltage V. gradually decreases toward the negative polarity power supply voltage vs8. And the output voltage V of the integrating circuit 3°. While the output current I0. of the SC circuit 10.20 is rising or falling, the output current I0. When I2 is in a balanced state and the combined current becomes 0, the output voltage V. The change in stops at that point, and then V.

does not change.

Now, suppose that the value of DC power supply v1 and the value of variable DC power supply v2 are set equal, then SC circuit 10.20 (1)
Assume that the capacitor p4 capacitor 1 i and the 21tD value "1+02" are set equal to each other. At this time, the SC circuit 1
0.20, the frequencies fs, fc of the two signals 5sSc
When they match, the combined current of current 11 and Δ is set to 0, and the output voltage of the integrating circuit 3 is V. is fixed to a certain value. When the voO value is fixed, the Seamit type oscillator circuit 5
The threshold voltage vH on the high level side, which is formed within 0, is also fixed.
Since VLI> is also fixed, the frequency f of the oscillation signal S8
s is also fixed.

Assume that I8 decreases from the state where the frequencies fs and fc match. When the frequency fs decreases, the above (1)
The absolute value of the SCC circuit 10 current 11 given by the formula becomes smaller. Then, the combined current of 1 and 2 has a positive polarity, and the output voltage of the integrating circuit 30 is V. is descending towards ■8s. Voltage V.

By falling toward vss, the voltage vIE obtained at the 0 point in the Seamit type oscillation circuit 50 decreases,
Since the Schmitt width (IVBI + IVLI) becomes narrower than before, the frequency fs of the oscillation output signal S6 in the Schmitt type oscillation circuit 50 increases. As the frequency 18 increases, the equivalent resistance value R1 of the SC circuit 10 becomes smaller, and the absolute value of the current factor gradually increases. Then, the combined current value of the electric current, I, decreases from the positive polarity toward the value of O, and becomes O when I6 matches fC. Therefore, when I8 drops, the output voltage V of the integrating circuit 30 until it matches fc. increases toward vDD, and stops rising when vo returns to its original value. When the frequency f of the oscillation output signal S matches fc, the rise of f also stops.

Assume that I8 increases from the state where the frequencies fs and fc match. As the frequency fs increases, the equivalent resistance value R1 of the SC circuit 10 given by the above equation (1) becomes smaller than before, and the absolute value of the current factor □ increases. Then, the combined current of the currents 11 and I2 becomes a negative polarity value, and the output voltage of the integrating circuit 30 becomes ■. It rises towards FivDD. As the voltage ■o increases, the threshold voltage vH on the high level side becomes higher than before, and the Schmitt width (IVH
I issue VLI) becomes wider than before, so the frequency f8 of the oscillation output signal S8 in the Schmidt type oscillation circuit 50 decreases. As the frequency f8 decreases, the equivalent resistance value R1 of the SC circuit 10 becomes thicker and the absolute value of the current becomes smaller one after another. Then, the combined current value of the current generator and I2 increases from negative polarity toward the value of O, and when I6 matches f, O
become. Therefore, when I8 increases, the output voltage V of the integrating circuit 30 increases until it matches fo. falls toward vss, and stops falling when vo returns to its original value, and the frequency 16 of the oscillation output signal Ss becomes f. When it matches, the fall of fs also stops.

That is, in this embodiment circuit, the value of the DC power supply V and the value of the variable DC power supply V2 are set equal, and the values of the capacitors 11 and 21 in the SC circuits 10 and 20 are set equal to each other. In this case, the frequency fB of the oscillation output signal S, is controlled to match the frequency fc of the signal Sc.

Next, we will explain the case of changing the setting of the variable DC power supply V.@First, if ■ is set higher than V□, the SC
Since the equivalent resistance value R2 of the circuit 20 is constant, this SC
Output current l of circuit 2θ! But it's getting bigger than before. At this time, the currents ■1 and I.

In order to balance the values and make the value of the combined current O, the absolute value of the output current of one SC circuit 10 needs to be larger than before.

By increasing the size of the electric current generator 2, the integration circuit 30
The output voltage V. falls toward vss, and after this, the frequency f of the oscillation output signal 3S of the Schmidt type oscillation circuit 50
s rises. This increase in frequency f8 continues until the absolute value of the output current I□ of the SC circuit 10 matches the absolute value of step 2. That is, when {circle around (2)} is set higher than vl, the frequency fs of the oscillation output signal S8 is controlled to be constant at a higher point than f.

Next, if ■2 is set lower than ■, the SC circuit 20
The output current factor 2 is now smaller than before.

At this time, in order to balance the currents 1 and 2 and make the value of the combined current O, contrary to the above, one of the SC circuits 1 and 2 must be balanced.
The absolute value of the zero output current I□ needs to be smaller than before.

As the current I2 becomes smaller, the output voltage V of the integrating circuit 30 decreases. increases toward vDD, and thereafter the frequency fB of the oscillation output signal Ss of the Schmitt type oscillation circuit 50 decreases. This decrease in frequency f8 is caused by the SC circuit 10
This continues until the absolute value of the output current 11 matches the absolute value of the output current 12. That is, when v2 is set lower than vl, the frequency fFil)if of the oscillation output signal Ss. It is controlled to be constant at a very low point.

By the way, the conditions for stabilizing the oscillation frequency fs in this example circuit are two SC circuits: 10°200, output current 1
1. The result is that the combined current value of I becomes 0. That is, this stability condition is given by the following equation.

I□+l2=0 (3) By substituting the relationship of resistance value R1+''2 given by the above equation (1) + (2) into the above equation (3), the following equation is obtained.

C1fB ・Vt +C2・fc−V2 =0−−(4
) Next, by summarizing the above equation (4) regarding fs, the following equation is obtained.

Here, we have previously assumed that C,=C, so f
8 is fo multiplied by V21y'','. Therefore, by adjusting the value of the variable DC power supply V, it is possible to create a signal S8 having a frequency 18 that is an arbitrary multiple of fc.

FIG. 4 shows a characteristic diagram of the above embodiment circuit when Cl=C2. The horizontal axis shows the frequency f of the oscillation signal Ss.
8, and the value of the variable DC power supply v2 is taken on the vertical axis. As shown in the figure, f8 has a linear relationship with ■2.

Here, the equivalent resistance values R,,R, in the two SC circuits 10.20 are given by C□
, if the value of C2 is constant, the frequency fs It is converted into a resistance R□rR2. The difference in the values of the resistors R, , R, is converted into a current, and this current is further converted into a voltage, and the oscillation frequency fs of the Schmitt type oscillator circuit 50 is adjusted according to this voltage, so that the frequency 18 can be adjusted stably and with high precision.

Furthermore, in the above explanation, the oscillation frequency fS is adjusted by changing the value of the variable DC power supply v2, but as is clear from the above equation (4), this is done by changing the value of the two SC circuits 10 and 20. The value C of capacitors 11 and 21 of
By changing the settings of 1 and C2, it is possible to adjust the frequency to a multiple according to the ratio. For example, by setting the value of the Youni capacitor 11.21 that satisfies the relationship n-01=02, the frequency of f8 can be adjusted to n times fc. Moreover, the value of n is not limited to an integer and can be set to a real number including a decimal, although this also applies when changing the variable DC power supply V2. Also, v in the second generation υ
l may be constructed from a variable DC power supply.

FIGS. 5 and 6 are circuit diagrams specifically showing two SC circuits 10 and 20 used in the circuit of the embodiment. In FIGS. 5 and 6, parts corresponding to those in FIG. 2 are designated by the same reference numerals. Furthermore, as the signal 5sSc, actually two signals having different phases as shown in the timing chart of FIG.
Phase signal S81. Ss□ or SC1, "'C2 is used.

The switches 12 to 15 in one SC circuit 10 having a negative equivalent resistance value are N-channel M
O8FET 71 to 74 each and P channel MO
It is composed of CMOS switches 82 to 85 each having 8FETs 75 to 78 connected in parallel.

The signal S81 in FIG. 7 is applied to the darts of the N-channel MO8FETs 71 and 74.
The signal Ss1 is supplied to the dates of ET 75 and ET 78 via a CMOS inverter 79, and the signal Ss2 in FIG.
, 77 are supplied with the signal S82 via a CMOS inverter 80, respectively.

In such a configuration, with the DC voltage v1 being supplied to the other end of the CMOS switch 83 and the ground potential being supplied to the other end of the CMOS switch 85, each of the CMOS switches 82 to 85 is controlled in accordance with the signals S81 and SS2. The case of switch control will be explained. Now, when the signal Ss2 is at a high level, the CMOS switches 83 and 84 are turned on.

At this time, charges of -0, *, are accumulated at the other end of the capacitor 11 (point f in FIG. 5). Next, when the signal Ss1 is at a high level, the CMOS switches 82 and 85 are turned on. At this time, a stop charge +C8·■1 flows into the point f from the ground point via the CMOS switch 85 so as to cancel out the negative charge that has been accumulated in advance.

Since this kind of operation is repeated every pfs for 1 second, if the direction of the current flowing from point f to the ground point via the CMOS switch 85 is positive, the value of the current flowing through this SC circuit is calculated by the following formula. is given by

SC with -I=C1・Vl・1s---(6)
Since the value of the equivalent resistance R in the circuit is the supply voltage v1 divided by the current l, this R is given by the following equation.

The right-hand side of this equation ('7) is the same as the right-hand side of (1) 2 above, and is 6
D. It can be seen that the SC circuit in FIG. 5 is a circuit having a negative equivalent resistance depending on the frequency fs.

The switches 22 to 25 in the other SC circuit 20 having a positive equivalent resistance value are N-channel M
O8FET 91 to 94 each and P channel MO
It is composed of CMOS switches 102 to 105 each having 8FETs 95 to 98 connected in parallel. And the above N-channel MO8FETs 91 and 93
The signal Sc1 in FIG. 7 is the P channel MO
The signal Sc1 is supplied to the darts of the 8FETs 95 and 97 via the CIVIOS inverter 99, and the signal So2 in FIG. 7 is supplied to the darts of the N-channel MO8FETs 92 and 94.
The signal Sc2 is supplied to darts 96 and 98 through a CMOS inverter 100, respectively.

In such a configuration, the CMOS switch 102
Supply DC voltage ■2 to the other end 7, CMOS switch 1
Each CMOS with ground potential supplied to the other end of 04.
The switches 102 to 105 are connected to the signal S. A case where the switch is controlled according to 11SC2 will be explained. When the signal Sc1 is now at a high level, the CMOS switch 102,
104 is turned on. At this time, a charge C2.2 is accumulated in the capacitor 2. Next, signal Sc2
When becomes a high level, the CMOS switch 103,
105 is turned on, and the charge that has been stored in capacitor 2 is discharged to the ground point.

That is, positive charges are drained from this circuit.

This kind of movement lasts for 1 second. Since this is repeated lJ fc times, if the direction of the current flowing from the other end of the capacitor 21 (point g in FIG. 6) to the ground point via the CMOS switch 104 is positive, the value I of the current flowing through this SC circuit is It is given by the following formula.

l=C2・v2・fc・・・・・・(8) Also, this SC
Since the value of the equivalent resistance R in the circuit is the supply voltage v2 divided by the above current I, R is given by the following equation.

The right side of equation (9) is the same as the right side of equation (2) above, and it can be seen that the SC circuit of FIG. 6 is a circuit having a positive equivalent resistance depending on the frequency fc.

FIG. 8 is a block diagram showing the configuration of another embodiment of the invention. In this embodiment circuit, a frequency dividing circuit 110 is added to the embodiment circuit of FIG. This frequency dividing circuit 1
Reference numeral 10 is for dividing the oscillation output signal Ss of the Schmitt type oscillation circuit 50 by n;
is a signal S (divided by n instead of the oscillation output signal S8)
controlled by.

According to such a configuration, the frequency f of the oscillation output signal S8
s is controlled to be constant at n times that in the case of FIG.

FIG. 9 is a circuit diagram showing a specific configuration of the frequency dividing circuit 110 in FIG. 8. In this frequency dividing circuit 110, the value of n is 8,
That is, this is an example in which the oscillation output signal S8 is divided by eight, and three D-type flip-flop circuits 11) to 113 are used.
This is a well-known structure consisting of The data input terminals of the three flip-flop circuits 111 to 113 are connected to their respective first output terminals Q, and the multi-stage connection is such that the second output ψjM of the preceding stage is connected to the clock input terminal CP of the succeeding stage. has been done. The oscillation output signal Ss from the Schmidt excavation circuit 50 is supplied to the clock input terminal of the first-stage flip-flop circuit 111, and the frequency-divided signal SS' is output from the second output terminal of the final-stage flip-flop circuit 113. is output. Note that in order to change the frequency division ratio n, the number of flip-flop circuits may be increased or decreased as necessary.

FIG. 10 is a block diagram showing the configuration of still another embodiment of the invention. This embodiment circuit includes a frequency divider circuit 110 similar to the circuit in FIG.
B has been added. The frequency dividing circuit 110 has a configuration similar to that shown in FIG. 9, for example, and divides the frequency of the oscillation output signal Ss of the Schmitt type oscillation circuit 50 by eight to output a signal 3W.

The one synchronizing circuit 126A is for synchronizing the signal St after being divided by eight with the signal S8 before being divided by eight, and the one SC circuit 10 is for synchronizing the signal St after being divided by eight with the signal S8 before being divided by eight.
20A output signal B.

controlled by The other synchronous circuit 120B is for synchronizing the reference signal Sc with the oscillation output signal Ss of the Schmitt type oscillation circuit 50, and the other SC circuit 20 is controlled by the output signal Sco of this synchronous circuit 120B. .

FIG. 11 shows the synchronous circuit 120A in FIG. 10.

120B is a circuit diagram specifically showing 120B. Note that the nine circuit configurations of the synchronous circuit 1'20 and 120B are the same except for the input signal. In the figure, 121 and 122 are start-up synchronized D-type flip-flop circuits, and the clock input terminals (cp
) is supplied with the oscillation output signal S8 from the Schmidt type oscillation circuit 50. The data input terminal of one of the flip-flop circuits 121 is supplied with the frequency-divided output signal Si of the frequency dividing circuit 110 in the case of the synchronous circuit 120A, and the signal Sc in the case of the synchronous circuit 120B. The signals q and U at the output terminal Q of the one 7-lip flop circuit 121 are supplied to the data input terminal of the other 7-lip flop circuit KS122 (7) and also to the inverter 123 . The output signal Q of the inverter 123 is the signal Q at the output terminal of the other 7-lip floating circuit 122.
2 to the NOR gate 124 in parallel.

The output signal X of the NOR dart 124 is supplied to the NAND dart 127 and the NOR gate 12B via two inverters 125 and 126 connected in series.

The output signal of the inverter 126 is passed through the four inverters 129 to 132 connected in cascade to the NAND
It is fed to gate 127 and NOR gate 12.8. Furthermore, the output signal of the NAND dart 127 is supplied to an inverter 133. and the above inverter 133
When the signal supplied to the flip-frog circuit 121 is Sf, the output signal is supplied to this SC circuit 1θ as a signal for controlling the switches 13 and 14 in the one SC circuit 10, and When the signal supplied to the circuit 12 is SC, it is supplied to the SC circuit 20 as a signal for controlling the switches 23 and 25 in the other SC circuit 2o. Above NOR dirt 1
When the signal 86 supplied to the frizzo flop circuit 12 is the output signal 28, the output signal 28 is output from the one SC circuit 1 when the signal 86 is supplied to the frizzo flop circuit 12.
0 is supplied to this SC circuit 1o as a signal for controlling the switches 12.15 in the flip-flop circuit 1.
When the signal supplied to 21 is Sc, the other SC
It is supplied to this SC circuit 20 as a signal for controlling switches 22, 24 in circuit 2o.

The synchronization circuit 120 or 120B configured as shown in FIG. 11 operates as follows. Assume now that, for example, the signal 34 has a phase shift as shown in FIG. 12 with respect to the oscillation output signal Ss from the Schmitt type oscillation circuit 5o.

The flip-flop circuits 121 and 122 output the output signal Ql in synchronization with the rising edge of the clock input signal, that is, the signal ss.
, Q2 are set to match the input signal, and the previous output level is maintained when the signal SC falls. Q2 changes as shown in FIG. Therefore, the output signal X of NOR dart 124
As a result, a pulse signal is obtained that is synchronized with the signal Ss and remains at a high level for only one cycle of ss. Inverters 129 to 132, 133 to which this signal X is supplied,
A circuit consisting of a NAND gate 127 and a NOR gate 128 uses this signal
Using the delay time of 2, a two-phase signal s81 "'82 with non-overlapping high level periods as shown in FIG.
The sc circuit l circle switch 12.15 controlled by the pair 5so1 is turned on for approximately one period of the signal ss. That is, the period during which the positive charge flows into the one SC circuit 10 is set to be a period corresponding to approximately one cycle of the signal S8. On the other hand, as an input signal, the signal S
Also in the synchronizing circuit 120B to which C is supplied, a pulse signal is obtained as the output signal X of the NOR dart 124, which is synchronized with the signal S8 and is at a high level only during one cycle of Ss. Further, from this signal X, a two-phase signal Sc1. as shown in FIG. A pair of signals 5c corresponding to S.
o1Sco2 is formed. Moreover, among these, the signal S'B in FIG. , the signal Sco corresponding to .

A switch 22゜2 in the SC circuit 20 controlled by
4 is turned on for approximately one cycle of signal S8. That is, the period during which positive charge flows out from the other SC circuit 20 is also set to a period corresponding to approximately one cycle of the signal SB, as in the case of the one SC circuit 10. As a result, in the embodiment circuit of FIG. 10, the above equation (4) holds true as is, thereby preventing the occurrence of errors when the oscillation frequency is relatively large. Moreover, as shown in FIG. 12, the signals S'801 and S'Bo2 (or S'co1 and ""
Since the high level periods of C02) do not overlap,
In the SC circuit 10, switches 12, 15 and 13° 14
are often turned on at the same time, and no error occurs in the current 11. This also applies to the SC circuit 20.

Note that this invention is not limited to the above embodiments, and various modifications are possible. For example, in the above embodiment circuit, the oscillation circuit whose oscillation frequency is adjusted according to the composite current value of the output currents of the SC circuit 10.20 is the Schmitt type oscillation circuit 50. Any functional oscillator circuit may be used. Furthermore, in the above embodiment circuit, one SC circuit lθ having a negative equivalent resistance is controlled by the signal Ss,
Although a case has been described in which control is performed using the signal SC of the other SC circuit 2 having a positive equivalent resistance, this may be configured to be controlled using the other signal.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an oscillation circuit that can stably and accurately generate a signal having a frequency that is an arbitrary multiple of a reference signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the general configuration of a speech recognition circuit, FIG. 2 is a circuit diagram showing the configuration of an embodiment of an oscillation circuit according to the present invention, and FIG. 3 is a Schmidt type circuit in the circuit shown in FIG. A waveform diagram showing the operation of the oscillation circuit, FIG. 4 is a characteristic diagram of the circuit shown in FIG. 2, and FIGS. 5 and 6 are circuit diagrams specifically showing the switched capacitor circuit used in the circuit shown in FIG. 2, respectively. 7 is a timing chart of signals used in the circuits of FIGS. 5 and 6, FIG. 8 is a block diagram showing the configuration of another embodiment of the present invention, and FIG. 9 is a part of the circuit of FIG. 8. 10 is a block diagram showing the structure of still another embodiment of the present invention. FIG. 11 is a circuit diagram showing the specific structure of a part of the circuit shown in FIG. 10. The figure is number 11
3 is a timing chart of the circuit shown in FIG. 10.20... Switched capacitor circuit (86 circuits), 1no, 21... Capacitor, 3o... Integrating circuit, 40... Voltage buffer circuit, 5o... Schmitt type oscillation circuit, 110... ...Frequency divider circuit, 120k. 120B...Synchronous circuit.

Claims (5)

[Claims] (1) A first means whose resistance value is set according to the frequency of the first signal and has a negative or positive equivalent resistance; or a second means having a negative equivalent resistance;
a third means for supplying a direct current bias to the second means to cause a direct current to flow respectively; and outputting an oscillation signal whose frequency is adjusted according to a combined current value of the output currents of the first and second means. An oscillation circuit comprising: a fourth means; and a fifth means for frequency-dividing the oscillation signal and feeding back the frequency-divided signal to the first means as the first signal. (2) A first means whose resistance value is set according to the frequency of the first signal and has a negative or positive equivalent resistance; or a second means having a negative equivalent resistance;
A third means for supplying a DC bias to the second means to flow a DC current, respectively, and outputting an oscillation signal whose oscillation frequency is adjusted according to the combined current value of the output currents of the first and second means. and a fifth means for dividing the frequency of the oscillation signal.
a sixth means for synchronizing the frequency-divided output signal of the fifth means with the oscillation signal and supplying the synchronized signal to the first means as the first signal; Second
an oscillation circuit comprising: seventh means for synchronizing the above signal with the oscillation signal and supplying the synchronized signal to the second means. (3) The oscillation according to claim 1 or 2, wherein the first and second means are respectively constituted by a switched circuit and a V-pass circuit including a signal shift circuit and a plurality of switches. circuit. (4) The third means includes a DC voltage source that supplies a constant DC voltage to one of the first and second means, and a DC voltage source that supplies a constant DC voltage to the other of the first and second means. 3. The oscillation circuit according to claim 1, further comprising a variable DC voltage source that supplies a DC voltage for adjusting the frequency of the oscillation signal. (5) The fourth means has first and second threshold voltages, and one of the threshold voltages is higher than the first and second threshold voltages.
Claim 1 comprising a Schmitt type oscillation circuit that is adjusted according to the combined current value of the output currents of the means.
The oscillation circuit according to item 1 or 2.