JPH03180774A - Circuit verifying device - Google Patents

Abstract

PURPOSE:To unnecessitate a confirmation of operation on an LSI sample and to attain a drastic reduction of time for developing the LSI by performing the confirmation of operation on a board of actual machine with the use of test pattern information confirmed on a main body of computer. CONSTITUTION:In the case a circuit verification is performed on the main body 1 of computer with the circuit diagram and test pattern thence the confirmation of operation is completed, the test pattern information is transferred to a data buffer board 3 through an additional board 2. By means of mounting the board 3 on the board of actual machine in advance through a socket 4, output pattern data are latched with an output latch 11 by a timing control part 10 and input data are latched with an input latch 9, then a comparison with the input pattern is made in a comparison part 8. When a noncoincidence is generated on this comparison, the noncoincidence is transmitted to the main body 1 of computer through the additional board 2.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a circuit verification device, and in particular to its
Regarding the configuration of the output circuit.

[Conventional technology]

Traditionally, in the development of semi-custom LSIs such as gate arrays and standard cells, the circuit is verified on a computer, that is, the circuit operation is confirmed, and then an LSI sample is manufactured based on the circuit connection information and becomes an evaluation board. It was installed on a semi-custom LSI board and a final function check of the LSI was performed.

[Problem to be solved by the invention]

The conventional final circuit verification method described above has the disadvantage that it requires a long development time because it is possible to confirm its operation on an actual board only after sample production.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate such drawbacks and provide a circuit verification device that makes it possible to check the operation of an LSI to be manufactured on an actual board immediately after completion of circuit verification on a computer.

[Means to solve the problem]

The configuration of the circuit verification device of the present invention is as follows:
A socket section connected to the SI, an input and output memory section that stores input/output data from this socket section, an output latch section that latches the output from this memory section, and a latch data from this output latch section. an additional board that outputs and inputs processed data; an input latch section that is connected to this additional board and that latches data from the additional board that performs circuit verification processing and outputs the processed data; and data from this manual latch section. and a comparison section that compares data from the input memory section and outputs a mismatch signal to the socket, and a timing control section that outputs timings of the memory section, the output latch section, and the input latch section. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a data buffer board used in an embodiment of the present invention, and FIG. 2 is a schematic configuration diagram of a system using FIG. 1. This system consists of a computer main body 1. Additional board 2. Data buffer board 3. It consists of socket 4.

On the computer main body, a circuit diagram for gate array development and a test pattern are input, and circuit verification (simulation) is performed. The additional board 2 is a board that inputs/outputs test pattern data etc. to the computer main body 1, the data buffer board 3 is a board that converts test patterns into digital signals and stores them, and the socket 4
is a socket for inputting/outputting test pattern information in the data buffer board 3 to the actual (evaluation) board. Cables 5.6 are used for these connections and carry test pattern information.

In the block diagram of the data buffer board in Figure 2,
Input memory 12. Computer main body 1 to output memory 13
Store test pattern information from . Input memory 1
The data in 2 is sequentially outputted to the comparison unit 8 under the control of the timing control unit ①0. The data input from the cable 6 is input to the timing control section I at the input latch 9.
The data is latched under the control of the input memory 12 and compared with the output data of the input memory 12 in the comparator 8. The data in the output memory 13 is latched by the output latch 11 under the control of the timing control section 10 and output to the cable 6.

FIG. 3 is a test pattern diagram illustrating the operations of FIGS. 1 and 2. The signal input to the computer is
The inputs (A, B) and outputs (C, D) are each converted into binary data of "1" or 0, and stored in the data buffer board 3.

In this case, circuit verification is performed using the circuit diagram and test pattern (Fig. 3) on the computer main body 1, and when the operation verification is completed, the test pattern information is transferred to the data buffer board 3 via the additional board 2. By attaching the data buffer board 3 to the actual machine board in advance through the socket 4, the output cover data is latched by the timing control unit 10, the output data is latched by the output latch 11, and the input data is latched by the input latch 9. A comparison with the input cover pattern is performed in section 8. If a discrepancy occurs as a result of this comparison, the discrepancy is transmitted to the computer main body via the additional board 2.

〔Effect of the invention〕

As explained above, the present invention eliminates the need to check the operation with LSI samples by checking the operation on the actual board using the test pattern information confirmed on the computer itself, and significantly shortens the LSI development period. There is an effect that it can be done.

[Brief explanation of drawings]

Fig. 1 is a block diagram around the data buffer board of an embodiment of the present invention, Fig. 2 is a schematic configuration diagram of the system including Fig. 1, and Fig. 3 explains the operation of Figs. 1 and 2. 91 which is a test pattern diagram to perform computer main body, 2.
...Additional board, 3...Data buffer board, 4.
...Socket, 5...Cable, 6...Cable,
7... Mismatched cable, 8... Comparison section, 9... Input latch, 10... Timing control section, 11... Output latch, 12... Input memory, 13... Output memory.

Claims (1)

[Claims] a socket part connected to an LSI to be subjected to circuit verification;
An input and output memory section that stores input/output data from this socket section, an output latch section that latches the output from this memory section, and an additional section that outputs the latch data from this output latch section and inputs processing data. a board, an input latch unit that is connected to the additional board and that latches data from the additional board that performs circuit verification processing and outputs the processed data, and an input latch unit that latches data from the input latch unit and the input memory unit. A circuit verification device comprising: a comparison section that compares and outputs a mismatch signal to the socket; and a timing control section that outputs respective timings of the memory section, the output latch section, and the input latch section.