JPH03181222A - Externally synchronizing programmable device - Google Patents

Abstract

PURPOSE:To easily obtain an externally synchronizing system with a small number of parts by comparing the phases of external and internal signals with each other, and generating the signals showing the gain, the loss and the coincidence of the phases or the frequencies between the external and internal signals. CONSTITUTION:A voltage controlled oscillation circuit 12 produces a signal SY having an oscillation frequency corresponding to the voltage of a signal SP outputted from a low pass filter 11. A 1/N dividing circuit 1b divides the signal SY into 1/N to outputs an internal signal S2. At the same time, a 1/M dividing circuit 1a divides a signal SG into 1/M and outputs an external signal S1. Then a phase comparator 3 detects the phase difference between the signals S1 and S2, and a signal corresponding to the phase difference is outputted from a charge pump circuit 4. This feedback control is automatically repeated so that the phase difference between both signals S1 and S2 is set at zero. Then the external synchronization is attained.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention enables a circuit designer to easily realize or modify any circuit according to desired circuit specifications, and also enables a circuit designer to easily realize or change an arbitrary circuit according to desired circuit specifications. The present invention relates to an externally synchronized programmable device capable of so-called externally synchronized operation in which an internal circuit is operated in synchronization with the phase and frequency of an externally synchronized programmable device.

[Conventional technology]

Conventionally, programmable logic devices have been used as devices that allow circuit designers to easily realize or modify circuits that meet desired circuit specifications.
Logic devices) are known.

This programmable logic device can realize an appropriate logic circuit with an AND-OR two-stage configuration by programming appropriate lattice points of the AND matrix and the OR matrix, and can also change the circuit by changing the program. Since it is also possible to redesign, it has excellent functions in terms of versatility.

Moreover, programmable logic devices do not only realize random logic, but also realize arbitrary sequential circuits by feeding back the output of the above-mentioned OR matrix or the output of the built-in flip-flop to the input terminal of the AND matrix. Therefore, it is suitable for use in control devices such as sequence controllers, various measuring instruments, etc.

Conventionally, a programmable logic device having a configuration as shown in FIG. 5 has been common. That is, in FIG.
In the figure, the input signal lines -L, which are generated from the vertical lines, and the product term lines, which are generated from the horizontal lines arranged to intersect these input signal lines, are 1. -1. and a logical product matrix 1 which can realize any logic circuit by appropriately programming the grid points formed at each of these intersections, and these product term lines 11 to 1. It is provided with an OR matrix (functionally indicated by multi-input OR gates OR5 to OR in the figure) connected via AND outputs (functionally indicated by -AND gates in the figure). Further, general-purpose input ports 11 to I4 for supplying logic signals from the outside to some of the input signal lines -L, a clock input terminal CLK for supplying clock signals, and logic An output port for outputting the output signal of the sum matrix (multi-input OR gate OR, ~OR, in the figure) to the outside, and a control signal for supplying a control signal for controlling the output timing of the output port. An input terminal CNT etc. are provided.

The configuration of the output port can be described as a representative output circuit related to the output terminal P1 by the logical sum (indicated by OR in the figure).
The output is a D-type flip-flop FF.

The output contact Q is connected to the output terminal P via the output buffer circuit B1.

Further, the clock contact of the flip-flop FF is wired so as to be supplied with a clock signal from the clock input terminal CLK via an input buffer circuit, and an output buffer circuit B.

is a flip-flop FF according to the logic level of the control signal supplied from the control signal input terminal CNT.

The output signal of the output terminal P1 is transferred to the output terminal P1, or the output terminal is placed in a high impedance state. Furthermore, the inverted output a of the flip-flop FF+ is connected to the input signal line through the buffer circuit FB,
It is wired so as to feed back to some of the input signal line groups of L. The output circuits related to the remaining output terminals P2 to P also have a similar configuration, and for example, these output circuits are formed in a cell structure.

Then, by programming appropriate lattice points of the AND matrix 1, a shift register, a counter, etc. are formed using the flip-flops formed in the output circuit, and at the same time, by feeding back the output to the AND matrix 1, Complex sequential controllers and various signal processing circuits can be realized.

[Problem to be solved by the invention]

By the way, it is known that an effective technical method for sequential controllers and signal processing circuits is to control various devices and perform signal processing by synchronizing the phase and frequency to follow the phase and frequency of a certain signal. It is being

According to this technical method, when two or more systems operate in synchronization with different frequencies, the phase of the signal transferred from one system is By operating the other system so as to follow the same frequency, the other system can be operated synchronously with respect to one system.

As a typical technical means for performing such so-called external synchronization, PLL (phase-1oc
kedloop) is known, and as an example of its application,
Applications include motor speed control systems, FM/AM transmission/reception systems, and measuring instruments that extract only the desired signal from noise, and PLL devices are being developed as ICs (integrated circuits).

However, conventional PLL devices were developed as dedicated devices for various applications, so
It is necessary to select a specific PLL device depending on the application, and a separate PLL device is required to make changes to the system.
There are problems such as inconveniences such as not being able to find a suitable PLL device to implement a desired system, and a low degree of freedom in system design.

The present invention has been made in view of such conventional problems, and enables external synchronization operation and allows a circuit designer to easily realize or modify any circuit that meets desired circuit specifications. The purpose is to provide a highly versatile externally synchronized programmable device.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a programmable logic having an AND matrix and an OR matrix that realizes an arbitrary logic circuit by programmatically connecting appropriate lattice points. compares the phase difference between the external signal and the internal signal formed by the logic circuit formed by the above program, outputs a signal indicating the phase difference, and determines whether the two phases match or mismatch. The present invention is a programmable IC device including at least a phase comparator circuit that supplies a signal shown to a predetermined input signal line of the AND matrix.

[Effect]

According to the present invention having such a configuration, by inputting an external signal supplied from the outside and an internal signal generated in an internal circuit realized by an internal programmable logic section to the phase comparator, the external signal and the internal signal are input to the phase comparator. Since it is possible to generate a difference signal indicating a delay or lead in phase or frequency between internal signals, an external synchronization type system such as a PLL etc. that applies feedback to the internal circuit so that this difference signal reaches a predetermined value is used. It can be realized easily and with a small number of parts.

Furthermore, by realizing a control circuit for controlling various devices in a programmable logic section according to a signal indicating whether the phases of both signals match or do not match, external synchronization type systems such as PLI can be easily and less complicated. This can be realized with a small number of parts.

Further, since the programmable logic section can form any circuit by programming appropriate lattice points, the degree of freedom in design is high and changes can be easily made.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

First, the structure will be explained based on FIG. In this example, it is formed as a single IC (integrated circuit device) by a CMO3 semiconductor process, and the signal lines consisting of the vertical lines in the figure, ~L6, and the lines that intersect with these signal lines. Product term lines 11 to I1. and a logical product matrix 1 which can realize any logic circuit by appropriately programming the grid points formed at each of these intersections, and these product term lines 1! , -1fi (functionally shown as an AND gate in the figure)
It is provided with an OR matrix (in the figure, functionally indicated by multi-input OR gates OR8 to ○R1, ○R8, and OR7) connected through.

Further, general-purpose input terminals 11 to IJ for supplying logic signals from the outside to some of the input signal line groups of the input signal lines to L, a clock input terminal CLK for supplying a clock signal CK, A control signal input terminal CNT and the like for supplying a control signal are provided. Then, the OR matrix (multi-input OR gates OR1 to OR, in the figure)
a plurality of output terminals P for outputting output signals to the outside;
An output boat with ~P1 is formed.

To represent the output circuit related to the output terminal P of the output boat, the logical sum (indicated by OR in the figure) output is D.
The output contact Q is connected to the output terminal P via the output sofa circuit B. Also, flip-flop FF,
The clock input terminal CK of B! is wired so that the clock signal from the clock input terminal CLK is supplied via a manual buffer circuit, and the output buffer circuit B! transfers the output signal of the flip-flop F FI to the output terminal P1 or puts it in a high impedance state depending on the logic level of the control signal supplied from the control signal input terminal CNT.

Furthermore, the wiring is such that the inverted output 0 of the flip-flop FF is fed back to a part of the signal input line group of the signal input lines .about.L via the buffer circuit FB. The output circuits related to the remaining output terminals Pi-Pi also have a similar configuration, and for example, these output circuits are formed in a cell structure.

Furthermore, 2 is an amplifier connected between the input/output terminals S1 and O32, and its input contact is connected to the clock input (CK) of the internal flip-flop.

3 is a phase comparator circuit, which consists of a logical sum matrix ○RX
The first signal SI output from the OR matrix O
Compares the phases between the second signals 32 output from R, and outputs logic signals Su and SD representing the phase difference, as well as a logic signal SLK indicating whether the phases of both signals match or do not match. Output.

A charge pump circuit 4 outputs the logic signal Su output from the phase comparison circuit 3 and a pulse-modulated digital signal SP corresponding to 30 to an output terminal Pn.

FIG. 2 shows a specific circuit example of the phase comparison circuit 3 and charge pump circuit 4. That is, the phase comparator circuit 3 includes a plurality of NAND gates, AND gates, inverter gates, and exclusive OR gates.
It is a digital phase comparator circuit consisting of
The rise time of the signal S2 with respect to the supplied signal S,
Logic signal SLl with a time width corresponding to the phase difference in the nozzle
and a logic signal S. When the phase of the signal Sl is ahead of the signal S2, the logic signal SD is at "H" level, and when the phase of the signal S1 is behind the signal S2, the logic signal SD is at "H" level.
Logic signal Su becomes "L" level.

Furthermore, AND game) 3a, exclusive OR gate 3b,
The circuit that detects the NAND gate 3c and the inverter gate 3d goes "H" when the phases of the signals S1 and St match.
When the levels and phases do not match, both signals S1 and St
It outputs a logic signal SLK that becomes "L" level in a range where the logic levels of the two terminals are different from each other. Further, the logic signal S□ is wired so as to be outputted via the output terminal PLK.

On the other hand, the charge pump circuit 4, as shown in FIG.
It is formed of a P-channel MOS transistor and an N-channel MOS transistor connected between the power supply contact VDII and the ground contact, and a logic signal SU is supplied to the gate contact of the P-channel MOS transistor, and the logic signal SU is supplied to the gate contact of the N-channel MOS transistor. Logic signal S to gate contact
, and their common node contact is connected to the output terminal Pn-+. Therefore, the logic signal S. When S is at "L" level and logic signal S is at "L" level, an output S of 'Hn level is generated, logic signal Su is at "H" level, and logic signal SD is at 'H' level.
In the case of a high level, an output SP of the "L" level is generated, and in the case of other combinations, the output terminal Pn is set in a high impedance state except in a transient state.

Furthermore, in FIG. 1, 5 is a D-type flip-flop, the logic signal S□ from the phase comparator circuit 3 is supplied to the data input contact, and the output signal S from the output contact Q is supplied via the bumper circuit 6. The human input signal IL of the logical product matrix 1, .
and Lm-2. Furthermore,
A signal SCK from a predetermined output of the AND matrix 1 (functionally represented by an AND gate 9) is fed to the clock (CK) input of the flip-flop.

FIG. 3 shows a circuit configuration when the externally synchronized programmable device of the embodiment having such a structure is applied to a PLL. That is, the part shown within the dotted line in FIG. 3 is the externally synchronized programmable device related to this embodiment, and by programming appropriate grid points of the AND matrix (see FIG. 1), 1/M Frequency dividing circuit 1a
, an L/N frequency dividing circuit 1b, and a signal processing circuit 1c.

Note that the 1/M frequency dividing circuit 1a is configured to input an external signal SG from the outside to the input terminal 1, for example.
Divide G by M to obtain a predetermined output of the OR matrix 0R1I
This is achieved by programming appropriate lattice points of the AND matrix so that the frequency-divided signal S1 is generated.

The 1/N frequency divider circuit 1b receives the signal S generated on the input signal line.
, is frequency-divided by N and the frequency-divided signal S2 is generated at a predetermined output ○Rv of the logical sum matrix by programming appropriate lattice points of the logical product matrix.

In the signal processing circuit IC, the output SL from the phase comparator circuit 3 is connected to an input signal line L m-1- via a flip-flop 5.
This is a circuit for forming various control signals by being transferred to L+w-2, and is formed by programming appropriate grid points between the human input signal lines L1-1L Yaw2 and the OR matrix.

Further, the clock signal generation circuit 10 has a logical product matrix 1
is formed by programming appropriate grid points such that the signal SCX is generated at the output of a predetermined AND matrix shown by AND gate 9 in FIG.

Furthermore, as an external circuit, as shown in FIG. 3, a low-pass filter (lag lead filter) 11 made up of a resistor and a capacitor is connected to the output terminal Pn, and the input/output terminal O3 is connected to the output terminal Pn.
, and O32, a voltage controlled oscillation circuit 12 including an amplifier 2 is constructed by connecting a crystal resonator, a variable capacitance diode, a resistor, a capacitor, etc. between The input contacts of circuit 12 are supplied.

According to the PLL circuit configured in this way, the voltage controlled oscillation circuit 12 generates a signal S with an oscillation frequency corresponding to the voltage of the signal S output from the low-pass filter 11, and
The frequency dividing circuit 1b divides the frequency of this signal S7 to 1/H to generate a signal S
Outputs 2. Also, the 1/M frequency dividing circuit 1a divides the signal S6 into M
The frequency is divided and a signal S1 is output. And phase comparator circuit 3
detects the phase difference between the signal S and the internal signal S2, and a signal corresponding to the phase difference is output from the charge pump circuit 4,
Furthermore, a signal S integrated by the low-pass filter 11 is output.

By automatically repeating the feedback control in this PLL circuit, the PLL circuit operates so that the phase difference between the signal S1 and the internal signal S2 becomes zero, and external synchronization with the external signal S is realized.

Figure 4 shows the phase comparator circuit in Figure 2 and the PL shown in Figure 3.
To explain the operation of the L circuit, when the phase of the signal S1 is delayed with respect to the signal S2, when the phase is ahead,
The signal waveforms at each contact are shown in a locked state where the phases completely match.

Here, as shown after 1200 μs, the signals S1 and 3
When the phases of the gates 2 and 2 match, a pulse-like so-called whisker occurs in the output signal SA of the AND gate 3a (see FIG. 2) in the phase comparison circuit 3, and the exclusive OR gate 3
Since such a pulse is not generated in the output signal SX of the output signal SX, the logic signal SLK finally generated in the phase comparator circuit 3
If the logic signal SLK including this whisker is directly supplied to the signal processing circuit IC based on the AND matrix, normal signal processing cannot be performed. However, in this embodiment, a flip-flop 5 for removing such unnecessary whisker-like pulses is built-in in advance, and this logic signal SLK is fed back into the AND matrix via the flip-flop 5, so that normal operation is possible. It is possible to perform various signal processing.

Thus, according to this embodiment, the conjunctive matrix (
By programming appropriate lattice points (see Figure 1), any circuit can be realized according to the program, and the logic signal detected whether the phases of the two signals match or do not match is supplied to the AND matrix. Since the phase comparator circuit is built-in in advance, it is extremely effective in realizing an externally synchronized system, and is highly versatile and can greatly improve the degree of freedom in design.

In the above embodiment, a case was explained in which the CMOS process was applied to manufacture, but the B1-CMOS process may also be used to form a phase comparator circuit capable of processing analog signals inside. .

〔Effect of the invention〕

As explained above, according to the present invention, by manually inputting an external signal supplied from the outside and an internal signal generated in an internal circuit realized by an internal programmable logic section to a phase comparator, the external signal can be input to the phase comparator. Since it is possible to generate a signal indicating lead, delay, or coincidence of phase or frequency between internal signals, an external synchronization type such as a PLL that applies feedback to a voltage controlled oscillation circuit so that this signal reaches a predetermined value is used. The system can be easily realized with a small number of parts.

In addition, since a control circuit for controlling various devices according to a signal indicating whether the phases of both signals match or do not match can be realized using a programmable logic section, a complicated external synchronization type system can be easily and reduced. This can be realized with a small number of parts.

Further, since the programmable logic section can form any circuit by programming appropriate lattice points, the degree of freedom in design is high and changes can be easily made.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram showing the configuration of an embodiment according to the present invention; Fig. 2 is a circuit diagram showing a specific circuit example of a phase comparator circuit; Fig. 3 is a PLL circuit using the device of one embodiment. A circuit diagram when the present invention is applied; FIG. 4 is a timing chart for explaining the operation of the PLL circuit shown in FIG. 3; FIG. 5 is a diagram illustrating the configuration of a conventional programmable logic system. Codes in the figure: 1; AND matrix Ia; ]/M frequency divider circuit 1bil/N frequency divider circuit 1C; signal processing circuit 2; amplifier 3; phase comparison circuit 3a; AND gate 3b; exclusive OR gate 3c; NAND gate 3d: Inverter gate 4; Charge pump circuit 5 Ni-clip flop 6; Buffer circuits 7a, 7b; Analog switch 9; One output lO of AND matrix; Clock signal generation circuit 11; Low-pass filter 12; Voltage controlled oscillation Circuit 13.15; Analog switch 14; Output sofa circuit 16; Inverter gate (outside

Claims (1)

[Claims] A programmable logic section having an AND matrix and an OR matrix for realizing an arbitrary logic circuit through program connections, and an internal signal formed by an external signal and a logic circuit formed by the program. at least a phase comparison circuit that compares the phase difference between the two and outputs a signal indicating the phase difference, and also supplies a signal indicating whether the phases of the two match or do not match to a predetermined input signal line of the AND matrix. An externally synchronized programmable device characterized by: