JPH03196698A - Printed wiring board having detecting part for insulating layer and the like - Google Patents

Printed wiring board having detecting part for insulating layer and the like

Info

Publication number
JPH03196698A
JPH03196698A JP33719189A JP33719189A JPH03196698A JP H03196698 A JPH03196698 A JP H03196698A JP 33719189 A JP33719189 A JP 33719189A JP 33719189 A JP33719189 A JP 33719189A JP H03196698 A JPH03196698 A JP H03196698A
Authority
JP
Japan
Prior art keywords
printed wiring
layer
insulating layer
wiring board
shield
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33719189A
Other languages
Japanese (ja)
Inventor
Shin Kawakami
川上　伸
Satoru Haruyama
春山　哲
Hirotaka Okonogi
弘孝 小此木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon CMK Corp
CMK Corp
Original Assignee
Nippon CMK Corp
CMK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon CMK Corp, CMK Corp filed Critical Nippon CMK Corp
Priority to JP33719189A priority Critical patent/JPH03196698A/en
Publication of JPH03196698A publication Critical patent/JPH03196698A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

PURPOSE:To enable accurate measurement of a film thickness of an insulating layer of a printed wiring board and characteristics of a shield layer through a checking land by providing a checking land of the insulating layer simultaneously with formation of the insulating layer and by providing two independent checking lands of the shield layer and a connection part between the both lands. CONSTITUTION:A printed wiring circuit 2 is formed on a substrate 1. A solder resist layer 4 is formed on the printed wiring circuit 2 and a shield layer 5 is formed on the solder resist layer 4. A checking land 3 of the solder resist layer 4 is provided simultaneously with formation of the solder resist layer 4. Two independent checking lands 14, 15 of the shield layer 5 and a connection part 17 between the both lands 14, 15 are provided simultaneously with formation of the shield layer 5. Since checking lands 3, 14, 15 are formed simultaneously with the insulating layer 4 and the shield layer 5 formed on the printed wiring circuit 2, it is possible to measure a film thickness of the insulating layer of the printed wiring board and characteristics of the shield layer accurately.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はプリント配線板に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to printed wiring boards.

〔従来の技術〕[Conventional technology]

従来プリント配線板は第３図および第４図に示す如く基
板１の片面または両面に設けた銅箔により所要のパター
ンから成るプリント配線回路２を形成するとともに電気
部品の接続あるいはその他の外部との電気的な接続のた
めの接続ランド３を残して絶縁層４をシルク印刷により
形成している。Conventional printed wiring boards, as shown in FIGS. 3 and 4, form a printed wiring circuit 2 consisting of a desired pattern using copper foil provided on one or both sides of a substrate 1, and also connect electrical components or other external connections. An insulating layer 4 is formed by silk printing, leaving a connection land 3 for electrical connection.

また、前記プリント配線回路２上側には必要に応して電
磁波シールド用のシールド層５を設けた場合にはさらに
このシールドＮ５上側に絶縁層（オーバーコート層）７
を設けることにより構成されている。尚６は接続ランド
３に設けたスルーホールである。Further, if a shield layer 5 for electromagnetic wave shielding is provided above the printed wiring circuit 2 as necessary, an insulating layer (overcoat layer) 7 is further provided above the shield N5.
It is constructed by providing the following. Note that 6 is a through hole provided in the connection land 3.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

さて、前記従来のプリント配線板１０における絶縁層４
．７はプリント配線回路２あるいはシールド層５の電気
特性、性能を大きく左右するとともにプリント配線板１
０自体の品質５性能、耐久性等を直接左右するもので、
通常製品としてプリント配線板ｌＯの抜き取り検査時に
絶縁層４，７の膜厚を検査しているが、その検査は絶縁
層４゜７の断面部分により検査している。Now, the insulating layer 4 in the conventional printed wiring board 10
．． 7 greatly influences the electrical characteristics and performance of the printed wiring circuit 2 or the shield layer 5, and also affects the printed wiring board 1.
The quality of 0 itself directly affects performance, durability, etc.
The film thicknesses of the insulating layers 4 and 7 are usually inspected during sampling inspection of the printed wiring board 10 as a product, and the inspection is performed using a cross-sectional portion of the insulating layer 4.7.

しかるに絶縁Ｍ４，７の断面部分は、プリント配線＋１
ｉ　１０のうちの単に基板ｌの上側に形成された絶縁層
４、あるいはシールド層５の上側に設けられた絶縁Ｎ７
の部分では膜厚に誤差が存在し、検査部分の計測が正確
であってもバラツキを生しプリント配線板１０の全体に
おいて性能あるいは耐久性上等要求される適切な絶縁層
の膜厚を計測することは不可能であった。However, the cross section of insulation M4, 7 is printed wiring +1
The insulating layer 4 formed simply on the upper side of the substrate l of i10 or the insulating layer N7 provided on the upper side of the shield layer 5
There is an error in the film thickness in the part, and even if the measurement of the inspection part is accurate, there will be variations, and it is necessary to measure the appropriate thickness of the insulating layer that is required for performance or durability in the entire printed wiring board 10. It was impossible to do so.

又、上述シールド層５のシールド効果を判定するにはシ
ールド層５の厚さと導電性とを知る必要を生ずる。しか
し、シールド層５は通常導電性インキのシルク印刷技法
による塗布であるため各プリント配線板においてシール
ド特性のばらつきが多いが、現在では特性検査の適切な
方法がなく、加えて通常はシールドＮ５上の全面にオー
バーコートＮ７を印刷塗布するため検査は不可能である
ことも一要因となっている。Furthermore, in order to determine the shielding effect of the shield layer 5, it is necessary to know the thickness and conductivity of the shield layer 5. However, since the shield layer 5 is usually coated with conductive ink using a silk printing technique, there are many variations in the shielding characteristics of each printed wiring board, but currently there is no appropriate method for testing the characteristics, and in addition, it is usually applied on the shield N5. Another factor is that inspection is impossible because overcoat N7 is applied by printing to the entire surface of the surface.

因って、本発明はか−る従来のプリント配線板における
絶縁層の膜厚計測上の欠点並びにシールド層の特性等の
検査上の欠点に鑑みて開発されたもので、プリント配線
板自体に何等の悪影響を与えずに計測および検査し得る
プリント配線板の提供を目的とするものである。Therefore, the present invention was developed in view of the shortcomings in measuring the film thickness of the insulating layer and the shortcomings in inspecting the characteristics of the shield layer in the conventional printed wiring board. The object of the present invention is to provide a printed wiring board that can be measured and inspected without causing any adverse effects.

〔課題を解決するための手段〕[Means to solve the problem]

本発明プリント配線板は基板の片面または両面にプリン
ト配線回路を設けるとともに絶縁層を介してシールド層
を設けて成るプリント配線板において、前記絶縁層の形
成と同時に絶縁層のチェック用ランドを設けるとともに
前記シールド層の形成と同時に２個の独立したシールド
層のチェック用ランドと両ランド間に接続部を設けるこ
とにより構成したことを特徴とするものである。The printed wiring board of the present invention is a printed wiring board in which a printed wiring circuit is provided on one or both sides of the board and a shield layer is provided via an insulating layer, in which a land for checking the insulating layer is provided simultaneously with the formation of the insulating layer. The present invention is characterized in that, simultaneously with the formation of the shield layer, two independent check lands of the shield layer and a connecting portion are provided between the two lands.

〔作　用〕[For production]

本発明プリント配線板は、プリント配線回路上側に形成
される絶縁層およびシールド層と同時にチェック用ラン
ドを形成し、当該チェック用ラントを介してプリント配
線板に形成された絶縁層の１１り厚およびシールド層の
特性を適確に計測し得る作用を有する。The printed wiring board of the present invention forms a check land at the same time as the insulating layer and the shield layer formed on the upper side of the printed wiring circuit, and the thickness of the insulating layer formed on the printed wiring board increases through the check runt. It has the ability to accurately measure the characteristics of the shield layer.

〔実施例〕〔Example〕

以下本発明プリント配線板の一実施例を図面とともに詳
細に説明する。Hereinafter, one embodiment of the printed wiring board of the present invention will be described in detail with reference to the drawings.

第１図は本発明プリント配線板の平面図、第２図ａは第
１図Ａ−Ａ拡大断面図、第２図すは第１図Ｂ−Ｂ拡大断
面図、第２図Ｃは第１図Ｃ−Ｃ断面図である。1 is a plan view of the printed wiring board of the present invention, FIG. 2a is an enlarged sectional view taken along the line AA in FIG. 1, FIG. It is a sectional view taken along the line C-C in FIG.

しかして、第１図のプリント配線板１０は前述した第３
図および第４図示のプリント配線板ＩＯと同時に基板１
の片面にプリント配線回路２を形成するとともにこのプ
リント配線回路２の上側にソルダーレジスト層４を介し
てシールドＮ５を形成することにより構成されている。Therefore, the printed wiring board 10 of FIG.
At the same time as the printed wiring board IO shown in the figure and the fourth figure, the board 1
A printed wiring circuit 2 is formed on one side of the printed wiring circuit 2, and a shield N5 is formed on the upper side of the printed wiring circuit 2 via a solder resist layer 4.

また、か＼るプリント配ｍＦｉｌＯの形成に当り、予め
、プリント配線Ｉ１５．１０の所要位置に、切取孔１１
を配孔した切取部１２を介してテストピース部１３を設
け、このテストピース部１３上側にもソルダーレジスト
層４の形成と同時にテストピース部１３上側の銅箔２０
上にソルダーレジスト層１６ａ、１６ｂを形成し、かつ
プリント配線板１００オーバーコート層７の形成に関連
して前記ソルダーレジスト層１６ｂ上側にオーバーコー
ト層ｚ８を施すものである。In addition, when forming the printed wiring mFilO, cut holes 11 are placed in advance at the required positions of the printed wiring I15.10.
A test piece part 13 is provided through the cutout part 12 in which holes are arranged, and at the same time the solder resist layer 4 is formed on the upper side of the test piece part 13, the copper foil 20 on the upper side of the test piece part 13 is also formed.
Solder resist layers 16a and 16b are formed thereon, and an overcoat layer z8 is applied above the solder resist layer 16b in connection with the formation of the overcoat layer 7 of the printed wiring board 100.

すなわち、テストピース部１３におけるソルダーレジス
ト層１６ａ、１６ｂおよびオーバーコートＭ１８は、そ
れぞれプリント配線ＦｉＩＯのソルダーレジスト［４お
よびオーバーコートＮ７の製造工程と同一工程にて形成
する。That is, the solder resist layers 16a and 16b and the overcoat M18 in the test piece portion 13 are formed in the same process as the manufacturing process of the solder resist [4 and overcoat N7 of the printed wiring FiIO, respectively.

特にテストピース部１３におけるソルダーレジスト層１
６ａ、２６ｂおよびオーバーコート層１８により絶縁層
のチェックランド層が形成されるが、その大きさについ
てはそれぞれの形成に当って自由に設計し得るが、Ｍ厚
計側の正確性を期する為に５　Ｘ　５　ＩＤｍ以上の大
きさに形成することが望ましい。Especially the solder resist layer 1 in the test piece part 13
6a, 26b and the overcoat layer 18 form a check land layer of an insulating layer. Although the size of the check land layer can be freely designed when forming each layer, in order to ensure accuracy on the M thickness gauge side, It is desirable to form it to a size of 5×5 IDm or more.

さらに、前記プリント配線板ｌｏ自体のプリント配線回
路２の形成と同時に前記テストピース部１３の銅箔２０
の一部を利用して、独立した２個のテスト用のランド１
４．１５を形成するとともに前記ソルダーレジスト層４
の形成と同時にテストピース部１３上側のテスト用のラ
ンド１４．１５を残してソルダーレジスト層２１を形成
し、さらに前記シールド層５の形成に関連してテスト用
のランド１４．１５間を接続するシールド回路１７を形
成し、かつ前記プリント配線板１０のオーバーコート層
７の形成に関連してオーバーコート層２２を施すもので
ある。Further, at the same time as the printed wiring circuit 2 of the printed wiring board lo itself is formed, the copper foil 20 of the test piece portion 13 is
two independent test lands 1 using a part of the
4.15 and the solder resist layer 4
Simultaneously with the formation of the test piece portion 13, a solder resist layer 21 is formed leaving test lands 14.15 on the upper side of the test piece portion 13, and further, in connection with the formation of the shield layer 5, the test lands 14.15 are connected. A shield circuit 17 is formed, and an overcoat layer 22 is applied in connection with the formation of the overcoat layer 7 of the printed wiring board 10.

すなわち、テストピース部１３におけるランド１４．１
５、ソルダーレジスト層２１、シールド回路１７および
オーバーコー１［２２は、それぞれプリント配線板１０
のプリント配線回路２、ソルダーレジスト層４、シール
ド層５およびオーバーコート層７の製造工程と同一工程
にて形成する。That is, the land 14.1 in the test piece portion 13
5, solder resist layer 21, shield circuit 17 and overcoat 1 [22 is printed wiring board 10]
It is formed in the same process as the manufacturing process of the printed wiring circuit 2, solder resist layer 4, shield layer 5, and overcoat layer 7.

特に、シールド回路１７の長さおよび幅については、予
めシールド回路１７の形成に使用される導電性インキ、
すなわち前記プリント配線板１゜のシールド層５の形成
に使用される導電性インキの組成における抵抗値に対応
する基準設定値と比較しｉ＋′）る長さおよび幅（体積
）例えば長さ１ｏＩＩＩ１１、幅５胴等のものとなるよ
うに設計して形成するものである。In particular, regarding the length and width of the shield circuit 17, the conductive ink used to form the shield circuit 17,
That is, the length and width (volume) are compared with the reference setting value corresponding to the resistance value in the composition of the conductive ink used to form the shield layer 5 of the printed wiring board 1°, for example, the length 1oIII11, It is designed and formed to have a width of 5 cylinders or the like.

尚、ランド１４．１５の一部は測定を可能とする為にオ
ーバーコートＪ！Ｊ２２の形成時に一部を露出せしめて
形成する。In addition, a part of land 14.15 is covered with an overcoat J! to enable measurement. When forming J22, a part thereof is exposed.

図中、３はプリント配線回路２における接続ランド、６
はスルーホールである。In the figure, 3 is a connection land in the printed wiring circuit 2, and 6 is a connection land in the printed wiring circuit 2.
is a through hole.

以上の構成から成るプリント配線板ＩＯによれば、当該
プリント配線板ＩＯのプリント配線回路２部分に形成さ
れるソルダーレジスト層４およびオーバーコート層７の
製造工程において同時に所定位置にチェック用ランドと
してのソルダーレジストＮ１６ａ、１６ｂ、および一方
のソルダーレジスト層１６ｂ上側にはオーバーコート層
１８をテストピース部１３上側に形成したので、か＼る
テストピース部１３におけるソルダレジスト層重６ａに
より前記プリント配線板１０のソルダーレジスト筋４の
膜厚並びにオーバーコート層１８によりオーバーコート
層７の膜厚をそれぞれ計測することができる。According to the printed wiring board IO having the above configuration, in the manufacturing process of the solder resist layer 4 and the overcoat layer 7 formed on the printed wiring circuit 2 portion of the printed wiring board IO, a check land is simultaneously placed at a predetermined position. Since the overcoat layer 18 is formed above the test piece part 13 on the solder resist N16a, 16b and one of the solder resist layers 16b, the solder resist layer 6a in the test piece part 13 makes the printed wiring board 10 The thickness of the overcoat layer 7 can be measured based on the thickness of the solder resist streaks 4 and the overcoat layer 18.

特に、前記実施例においては、切取部１２を介してテス
トピース部１３を設け、このテストピース部１３に前記
絶縁層のチェック用ランドを設けたので計測の必要性に
応して、テストピース部１３をプリント配線板ｌＯより
切取部１２を介して切取り、か＼るテストピース部１３
のチェック用ンド層を切断してその切断面にて前記両Ｎ
１６　ａ　。In particular, in the above embodiment, the test piece part 13 was provided through the cutout part 12, and the test piece part 13 was provided with a land for checking the insulating layer. 13 is cut out from the printed wiring board lO through the cutout part 12, and the resulting test piece part 13 is
The check layer is cut and the above-mentioned N
16 a.

１６ｂ、１Ｂの各膜厚を計測することが可能で、プリン
ト配線板ｌＯを無駄にすることなく計測が可能である。It is possible to measure each film thickness of 16b and 1B, and measurement is possible without wasting the printed wiring board IO.

又、計測方法によっては非接触の膜厚形を使用すること
により、切断面による計測のみに限らない膜厚の計測も
可能であって、か−る方法の採用によれば、前記テスト
ピース部１３の両層１６ａ。Furthermore, depending on the measurement method, by using a non-contact film thickness gauge, it is possible to measure the film thickness not only by measuring the cut surface. 13 both layers 16a.

１６ｂ、１８を切断することのない計測の実施が可能で
ある。It is possible to carry out measurements without cutting 16b, 18.

さらに、前記プリント配線板１０自体のシールド層５に
ついては、当＝亥シールド層５の上側にはオーバーコー
ト層７を形成してしまうために、オーバーコート［７を
被覆されてしまったシールド層５の膜厚および所要のシ
ールド特性を発揮し得るものであるか否かの直接的な検
査が不可能であるが、本発明プリント配線板１０の場合
には、前記シールド層５の形成と同一工程、すなわち同
一形成条件（同一の組成から成る導電性インキによる同
一の条件によるシルク印刷等）による膜厚のシールド回
路１７が形成されるので、かかるシールド回路１７の電
気的な抵抗値をランＦ１４１５を介して測定することが
可能である。Furthermore, regarding the shield layer 5 of the printed wiring board 10 itself, since the overcoat layer 7 is formed on the upper side of the shield layer 5, the shield layer 5 covered with the overcoat [7] However, in the case of the printed wiring board 10 of the present invention, the same process as that for forming the shield layer 5 is performed. That is, since the shield circuit 17 is formed with the same film thickness under the same formation conditions (silk printing under the same conditions with conductive ink having the same composition, etc.), the electrical resistance value of the shield circuit 17 is determined by the run F1415. It is possible to measure via

従って、この測定値を予め同一組成の導電性インキによ
り形成された所定の膜厚、長さ（体積）における基準設
定値と比較することにより、プリント配線板１０におい
て形成されたシールド層５の特性を間接的に検知するこ
とができる。Therefore, by comparing this measured value with a standard set value at a predetermined film thickness and length (volume) formed using conductive ink of the same composition, the characteristics of the shield layer 5 formed on the printed wiring board 10 can be determined. can be detected indirectly.

しかして、前記実施例の場合には特にテストビス部１３
にチェック用ランドとしてのソルダーレジスト層１６ａ
、１５１）とオーバーコート層１８およびランド１４．
１５と両ランド１４１５間にシールド回路１７を設けた
が、予めプリント配置１ｉ１０のプリント配線回路２の
配設部の所定位置に前記構成の絶縁層およびシールド層
の計測、検査部を設けることにより実施することも可能
である。Therefore, in the case of the above embodiment, especially the test screw portion 13
Solder resist layer 16a as a check land
, 151), overcoat layer 18 and land 14.
The shield circuit 17 was provided between the land 15 and both lands 1415, but this was implemented by providing a measurement and inspection section for the insulating layer and shield layer of the above structure in advance at a predetermined position of the placement section of the printed wiring circuit 2 of the printed layout 1i10. It is also possible to do so.

イリし、か−る構成の場合には、プリント配線板１０の
ソルダーレジスト層４およびオーバーコート層７等の絶
Ｓ！層の膜厚およびシールド層の特性を適確に計測し得
る位置を選択した実施が要求される。However, in the case of such a configuration, the solder resist layer 4, overcoat layer 7, etc. of the printed wiring board 10 are completely damaged! It is required to select a location where the thickness of the layer and the characteristics of the shield layer can be accurately measured.

尚、チェック用−７７ド１６ａ、１６ｂ、１８の配設個
数およびランド１４．＋５、シールド回路】７について
は一箇所に限らず複数箇所に配設して実施することによ
り、膜厚計測および特性検査をプリント配線板の全体に
おいて把握し得る利点を有する。In addition, the number of check-77 doors 16a, 16b, 18 and lands 14. +5, Shield circuit] With regard to 7, there is an advantage that film thickness measurement and characteristic inspection can be performed on the entire printed wiring board by disposing the shield circuit not only at one location but at multiple locations.

〔発明の効果〕〔Effect of the invention〕

本発明プリント配線板によれば予め設定されたチエ、り
用ランＩ′およびランドとシールド回路を介してプリン
ト配線板の製造工程における絶縁層の膜厚およびシール
ド層の特性をａ確に計測することができる。According to the printed wiring board of the present invention, the film thickness of the insulating layer and the characteristics of the shield layer in the manufacturing process of the printed wiring board can be accurately measured through the preset wire run I' and the land and the shield circuit. be able to.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明プリント配線板の平面図、第２図ａは第
１図Ａ−Ａ拡大断面図、第２図すは第１図Ｂ−Ｂ拡大断
面図、第２図Ｃは第１図Ｃ−Ｃ断面図、第２図ｄは第１
図Ｄ−Ｄは拡大断面図、第３図は従来のプリント配線板
の平面図、第４図は第３図Ａ−Ａ断面図である。 １・・・基板 ２・・・プリント配線回路 ３・・・接続ランド ４・・・ソルダーレジスト ５・・・シールド層 Ｇ・・・スルーホール ７・・オーバーコート層 Ｏ・・・プリント配線板 】・・・切取孔 ２・・・切取部 ３・・・テストピース部 ４．１５・・・ランド ６ａ、　　１６ｂ・・ツルグーレジスト層７・・・シー
ルド回路 ８・・・オーバーコート層 ０・・・銅箔 第２図1 is a plan view of the printed wiring board of the present invention, FIG. 2a is an enlarged sectional view taken along the line AA in FIG. 1, FIG. Figure C-C sectional view, Figure 2 d is the first
DD is an enlarged cross-sectional view, FIG. 3 is a plan view of a conventional printed wiring board, and FIG. 4 is a cross-sectional view taken along line A-A in FIG. 1... Board 2... Printed wiring circuit 3... Connection land 4... Solder resist 5... Shield layer G... Through hole 7... Overcoat layer O... Printed wiring board] ... Cutout hole 2 ... Cutout section 3 ... Test piece section 4.15 ... Lands 6a, 16b ... Turtle resist layer 7 ... Shield circuit 8 ... Overcoat layer 0 ...・Copper foil diagram 2

Claims (4)

【特許請求の範囲】[Claims] （１）基板の片面または両面にプリント配線回路を設け
るとともに絶縁層を介してシールド層を設けて成るプリ
ント配線板において、 前記絶縁層の形成と同時に絶縁層のチェック用ランドを
設けるとともに前記シールド層の形成と同時に２個の独
立したシールド層のチェック用ランドと両ランド間に接
続部を設けることにより構成したことを特徴とする絶縁
層等の検査部を有するプリント配線板。(1) In a printed wiring board in which a printed wiring circuit is provided on one or both sides of a board and a shield layer is provided via an insulating layer, a land for checking the insulating layer is provided at the same time as the formation of the insulating layer, and the shield layer is provided with a land for checking the insulating layer. What is claimed is: 1. A printed wiring board having an inspection section for an insulating layer, etc., characterized in that the check land of two independent shield layers and a connection section are provided between both lands at the same time as the formation of the board. （２）前記絶縁層のチェック用ランドは前記プリント配
線回路部の所要位置に配置して成る請求項１記載の絶縁
層等の検査部を有するプリント配線板。(2) A printed wiring board having a part for inspecting an insulating layer or the like according to claim 1, wherein the land for checking the insulating layer is arranged at a predetermined position of the printed wiring circuit part. （３）前記絶縁層のチェック用ランドは前記基板の切取
部を介して形成したテスト用ピース部に形成して成る請
求項１記載の絶縁層等の検査部を有するプリント配線板
。(3) A printed wiring board having an inspection section for an insulating layer or the like according to claim 1, wherein the check land for the insulating layer is formed on a test piece section formed through a cutout section of the substrate. （４）前記絶縁層のチェック用ランドは５ｍｍ×５ｍｍ
以上の面積を備えて成る請求項１記載の絶縁層等の検査
部を有するプリント配線板。(4) The check land of the insulating layer is 5 mm x 5 mm.
2. A printed wiring board having an inspection section such as an insulating layer according to claim 1, which has an area equal to or more than 100 .ANG.
JP33719189A 1989-12-26 1989-12-26 Printed wiring board having detecting part for insulating layer and the like Pending JPH03196698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33719189A JPH03196698A (en) 1989-12-26 1989-12-26 Printed wiring board having detecting part for insulating layer and the like

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33719189A JPH03196698A (en) 1989-12-26 1989-12-26 Printed wiring board having detecting part for insulating layer and the like

Publications (1)

Publication Number Publication Date
JPH03196698A true JPH03196698A (en) 1991-08-28

Family

ID=18306302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33719189A Pending JPH03196698A (en) 1989-12-26 1989-12-26 Printed wiring board having detecting part for insulating layer and the like

Country Status (1)

Country Link
JP (1) JPH03196698A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102630370B1 (en) * 2023-02-27 2024-01-29 주식회사 두성테크 Substrate structure for pba manufacturing and pba manufacturing method using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102630370B1 (en) * 2023-02-27 2024-01-29 주식회사 두성테크 Substrate structure for pba manufacturing and pba manufacturing method using the same

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