JPH03201464A - Semiconductor ceramic package - Google Patents

Semiconductor ceramic package

Info

Publication number
JPH03201464A
JPH03201464A JP1340322A JP34032289A JPH03201464A JP H03201464 A JPH03201464 A JP H03201464A JP 1340322 A JP1340322 A JP 1340322A JP 34032289 A JP34032289 A JP 34032289A JP H03201464 A JPH03201464 A JP H03201464A
Authority
JP
Japan
Prior art keywords
hole
ceramic
package
coating layer
ceramic package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1340322A
Other languages
Japanese (ja)
Other versions
JP2546400B2 (en
Inventor
Toru Kamata
徹 鎌田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1340322A priority Critical patent/JP2546400B2/en
Publication of JPH03201464A publication Critical patent/JPH03201464A/en
Application granted granted Critical
Publication of JP2546400B2 publication Critical patent/JP2546400B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To keep a semiconductor ceramic package airtight by a method wherein the through-hole of the semiconductor ceramic package is covered with a ceramic coating layer. CONSTITUTION:A ceramic substrate 11 is provided with a through-hole 12, and a metallized layer 13 is provided to the inner face of the through-hole 12 so as to electrically connect wirings together formed on the front and the rear side of the substrate 11. The through-hole 12 is closed by a ceramic coating layer 14. A package can be kept airtight by covering the through-hole 12 with the ceramic coating layer 14. The ceramic coating layer 14 is an electrical insulator and can be formed through a screen printing so as to cover through- holes.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高密度実装に適した半導体用セラミックパッケ
ージに関し、特にスルーホールを有する半導体用セラミ
ックパッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ceramic package for semiconductors suitable for high-density packaging, and particularly to a ceramic package for semiconductors having through holes.

〔従来の技術〕[Conventional technology]

第４図、第５図はこの種の半導体用セラミックパッケー
ジを示すそれぞれ縦断面図、平面図である。FIGS. 4 and 5 are a longitudinal sectional view and a plan view, respectively, showing this type of semiconductor ceramic package.

この種の半導体用セラミックパッケージは第４図、第５
図に示すように、セラミック基板３１に設けられたスル
ーホール３２がリード端子３６とそれをセラミック基板
３１に取り付けるためのＡＵｌ　Ｃｕロウ３５によって
密封され気密性が保持される構造となっていた。This type of semiconductor ceramic package is shown in Figures 4 and 5.
As shown in the figure, a through hole 32 provided in a ceramic substrate 31 was sealed by a lead terminal 36 and an AUL Cu solder 35 for attaching it to the ceramic substrate 31, thereby maintaining airtightness.

（発明が解決しようとする課題〕 上述した従来の半導体用セラミックパッケージは、セラ
ミック基板の表裏両面のメタライズパターンを電気的に
導通しているスルーホールをリード端子でおおうように
ＡＵｌ　Ｃｕロウ付けしている構造となっているので、
リード幅は少くともスルーホール径よりも大きく殺到さ
せるを得すリード端子のピッチを小さくすることに限界
がありパッケージの多ピン化、高密度実装対応への障害
になるという欠点があり、またパッケージスルーホール
とリード端子の積置的ズレによりスルーホールを覆いき
れず気密性不良を生じやすいという欠点もある。(Problems to be Solved by the Invention) The conventional ceramic package for semiconductors described above is made by soldering AUL Cu so that the through holes that electrically conduct the metallized patterns on both the front and back sides of the ceramic substrate are covered with lead terminals. Because it has a structure that
The lead width must be at least larger than the through-hole diameter, but there is a limit to reducing the pitch of the lead terminals, which is an obstacle to increasing the number of pins in the package and supporting high-density mounting. Another drawback is that the through holes cannot be completely covered due to misalignment of the through holes and lead terminals, resulting in poor airtightness.

本発明は上記の欠点に鑑み、高密度実装に有利で、気密
性を確保するのに有利な半導体用セラミツクパッケージ
を提供することを解決すべき課題とする。In view of the above-mentioned drawbacks, the present invention aims to provide a ceramic package for semiconductors that is advantageous for high-density packaging and that is advantageous for ensuring airtightness.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体用セラミックパッケージは、全てのスル
ーホールの少くとも片側に、スルーホール部の気密性を
保持するようにセラミックコーティング層を形成してい
る。In the semiconductor ceramic package of the present invention, a ceramic coating layer is formed on at least one side of all the through holes so as to maintain airtightness of the through hole portions.

〔作用］ スルーホールがセラミック」−ティング層で覆われてい
るので、リード端子は小さくできかつ気密性も確実とな
る。[Function] Since the through hole is covered with a ceramic layer, the lead terminal can be made small and airtightness is ensured.

（実施例） 次に、本発明の実施例について図面を参照して説明する
。(Example) Next, an example of the present invention will be described with reference to the drawings.

第１図は本発明の半導体用セラミックパッケージの第１
の実施例を示す縦断面図、第２図は第１図の実施例が適
用された半導体用セラミックパッケージ全体を示す図で
ある。FIG. 1 shows the first ceramic package for semiconductors of the present invention.
FIG. 2 is a longitudinal sectional view showing an embodiment of the present invention, and FIG. 2 is a diagram showing an entire semiconductor ceramic package to which the embodiment of FIG. 1 is applied.

セラミック基板１１はスルーホール１２を有し、スルー
ホール１２の内側面にはメタライズ層１３がセラミック
基板１１の上下面の配線を電気的に導通するよう設けら
れている。スルーホール１２はセラミックコーティング
層１４によって閉じられている。スルーホール１２をセ
ラミックコーティング層１４で覆うことによってパッケ
ージの気密性が第２図のように確保されている。また、
セラミックコーティング！１１４は電気絶縁体であり、
複数のスルーホールを一括して覆うようにスクリーン印
刷法により形成することができる。The ceramic substrate 11 has a through hole 12, and a metallized layer 13 is provided on the inner surface of the through hole 12 so as to electrically connect the wiring on the upper and lower surfaces of the ceramic substrate 11. The through hole 12 is closed by a ceramic coating layer 14. By covering the through hole 12 with a ceramic coating layer 14, the airtightness of the package is ensured as shown in FIG. Also,
Ceramic coating! 114 is an electrical insulator;
It can be formed by a screen printing method so as to cover a plurality of through holes all at once.

第２図は本発明の第２の実施例を示す縦断面図である。FIG. 2 is a longitudinal sectional view showing a second embodiment of the invention.

セラミック基板１１のスルーホール１２はセラミックペ
ースト焼成体２４によって埋められた構造とする。この
実施例ではスルーホール径が比較的大きい場合でも確実
に気密性を確保できるという利点がある。The through hole 12 of the ceramic substrate 11 is filled with a ceramic paste fired body 24. This embodiment has the advantage that airtightness can be ensured even when the diameter of the through hole is relatively large.

（発明の効果） 以上説明したように本発明は、半導体用セラミックパッ
ケージのスルーホールをセラミックコーティング層によ
って覆うことにより気密性を確保する構造をとっている
ため、パッケージのリード端子の取り付はピッチはスル
ーホール径とは無関係に短縮化することが可能でありパ
ッケージの多ビン化に対応でき高密度実装を容易にする
効果があり、またセラミックコーティング層によりスル
ーホールを覆うあるいは埋める工程０よ大盪、バッチ処
理が可能であり、製造歩留りも良く安価なコストでパッ
ケージを製造することができるという効果もある。(Effects of the Invention) As explained above, the present invention has a structure that ensures airtightness by covering the through holes of a semiconductor ceramic package with a ceramic coating layer. can be shortened regardless of the through-hole diameter, making it possible to accommodate a large number of package bins, facilitating high-density packaging, and eliminating the process of covering or filling the through-holes with a ceramic coating layer. (2) Batch processing is possible, the manufacturing yield is good, and packages can be manufactured at low cost.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の半導体用セラミックパッケージの第１
の実施例を示す縦断面図、第２図は第１図の実施例を応
用したパッケージの全体を示す平面図、第３図は本発明
の第２の実施例を示す縦断面図、第４図は従来例の縦断
面、第５図は従来例の平面図である。 １・・・セラミック基板、 ２・・・スルーホール、 ３・・・メタライズ層、 ４・・・セラミックコーティング層、 ５・・・へｇ／Ｃｕロウ、 ６・・・リード端子。FIG. 1 shows the first ceramic package for semiconductors of the present invention.
2 is a plan view showing the entire package to which the embodiment of FIG. 1 is applied; FIG. 3 is a longitudinal sectional view showing the second embodiment of the present invention; FIG. The figure is a longitudinal section of the conventional example, and FIG. 5 is a plan view of the conventional example. DESCRIPTION OF SYMBOLS 1... Ceramic board, 2... Through hole, 3... Metallized layer, 4... Ceramic coating layer, 5... G/Cu wax, 6... Lead terminal.

Claims (1)

【特許請求の範囲】 １、スルーホールを有する半導体用セラミックパッケー
ジにおいて、 全てのスルーホールの少なくとも片側に、スルーホール
部の気密性を保持するようにセラミックコーティング層
を形成したことを特徴とする半導体用セラミックパッケ
ージ。[Claims] 1. A semiconductor ceramic package having through-holes, characterized in that a ceramic coating layer is formed on at least one side of all the through-holes so as to maintain airtightness of the through-hole portions. Ceramic package for.
JP1340322A 1989-12-28 1989-12-28 Ceramic package for semiconductor Expired - Lifetime JP2546400B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1340322A JP2546400B2 (en) 1989-12-28 1989-12-28 Ceramic package for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1340322A JP2546400B2 (en) 1989-12-28 1989-12-28 Ceramic package for semiconductor

Publications (2)

Publication Number Publication Date
JPH03201464A true JPH03201464A (en) 1991-09-03
JP2546400B2 JP2546400B2 (en) 1996-10-23

Family

ID=18335837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1340322A Expired - Lifetime JP2546400B2 (en) 1989-12-28 1989-12-28 Ceramic package for semiconductor

Country Status (1)

Country Link
JP (1) JP2546400B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61288446A (en) * 1985-06-17 1986-12-18 Fujitsu Ltd High-speed ic package structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61288446A (en) * 1985-06-17 1986-12-18 Fujitsu Ltd High-speed ic package structure

Also Published As

Publication number Publication date
JP2546400B2 (en) 1996-10-23

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