JPH03201712A - Clamp circuit - Google Patents

Abstract

PURPOSE:To eliminate a DC step difference caused by clamping by detecting the emitter current of a 1st output emitter follower of a pre-stage circuit for a clamp capacitor to control the emitter current of a 2nd emitter follower of opposite polarity provided on the pre-stage of the 1st output emitter follower. CONSTITUTION:A transistor(TR) Q3 and a current mirror CM are added to a conventional clamp circuit. That is, an input IN is supplied to the base of the TR Q3 whose collector connects to a power supply VCC and its emitter connects to the base of a TR Q2. Moreover, the collector of the TR Q2 connects to the input of the current mirror CM and the emitter of the TR Q3 connects to the output of the current mirror CM. Thus, a current entirely equal to the current flowing to the TR Q2 flows to the emitter of the TR Q3 for the clamping period and the outside of the clamping period. Since a DC step difference of the same level as that caused in the TR Q2 in opposite polarity is caused at the time of clamping, both the differences are cancelled together.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a clamp circuit for a video signal processing circuit used in, for example, a video camera.

(Prior Art) Generally, a pedestal clamp circuit of a video signal processing circuit used in a video camera is configured as shown in FIG. 4. This circuit consists of a clamp capacitor C and a pedestal clamp circuit PC.
The output OUT is fixed at a constant potential during the clamp period by the clamp pulse CP applied to the clamp pulse CP, and the potential difference between the input IN and the output OUT is sampled to the clamp capacitor C and held outside the clamp period. This is for determining the transmission level.

FIG. 5 shows a specific example of the circuit.

In the figure, the collector of the clamping transistor QI is connected to the reference f'r1 source VCC, the base is grounded via the dependent voltage iV+, and the emitter is connected to the dependent current source ! 1
It is grounded through the capacitor C1 and connected to one end of the clamp capacitor C1 and the output OUT.

Also, the other end of clamp capacitor C1 is PNP) transistor Q
It is connected to the reference power supply VCC via a current source I2. Transistor Q2
The collector of is grounded and the base is connected to the input IN. Note that the output impedance of the circuit in front of the input IN in FIG. 5 is preferably zero, but it is not zero in the actual circuit, so in order to take this effect into account, in FIG. Add an emitter follower. Further, the voltage/current sources V, , 11 are controlled by a clamp pulse CP, and the voltage source v1 is fixed to keep the output at a constant potential during the clamp period, and is set to a low potential that cuts off the transistor Q1 outside the clamp period. Fixed to keep. The current &911 causes a constant current to flow during the clamp period, and is turned off during the clamp period to cut off the transistor QI.

Here, consider a case where there is a leakage current at the output OUT. For example, when an emitter follower is connected to the output OUT for transmission to the next stage circuit, a base current flows. Even if the base current is compensated, it is difficult to reduce it to zero. In this case, in a steady state, in the case of an emitter follower of an NPN transistor, the charge discharged from the clamp capacitor C1 due to leakage current is discharged from the transistor Q1 during the clamp period to maintain balance. Since the current due to charging and discharging at this time changes the current density of the transistor Q2, a step is created in the output between the clamp period and other times, which causes errors in current transmission.

Now, let's consider how much of an output step difference there will be if there is a leakage current of 0.5 μA. Assuming that the clamp period is 2 μSee during one horizontal scanning period (Φ [i3.5 (i μsec)), the charging current flowing into the emitter of transistor Q2 during the clamp period is 0.5 μA.
x 83.58μsec / 2μsec : 15
．． It becomes 9μ＾. If the current of current source I2 is 200μA, the DC step is V7-fln (200μA +15.9μ^/20
0u^)=2. It becomes hV. Here, it is expressed as VT-kT/q, where k-Portzmann's constant, T-absolute temperature, and q-electron cable length. A value of 2.0 mV is an unacceptable value because it will result in color shift when a color difference signal is handled at a low power supply voltage of 5 V, for example. If the current of the current 912 is increased in order to reduce this level difference, the current consumption will increase, which is not preferable. Transistor Q2 is a PNP transistor, and I
If an attempt is made to configure the emitter within C, the knee current will be small, so in order to lower the current density, the emitter area must be increased. It is possible to lower the impedance by making the output stage a feedback type, but this increases the number of elements and is disadvantageous in terms of frequency characteristics. Furthermore, if base current compensation is performed to reduce leakage current, the number of elements will increase, and there is a limit to the compensation ability.

(Problems to be Solved by the Invention) In the above-described conventional clamp circuit, if the output impedance of the circuit preceding the clamp capacitance is not small, a DC level difference will occur in the output between the clamp period and other times. In order to eliminate this problem, it is possible to increase the current of the current source I2, but this is not preferable because the current consumption increases. Also, transistor Q2
If an attempt is made to configure this in an IC as a PNP type, a problem arises in that the knee current is small and the emitter area must be increased in order to lower the current density. Making the output stage a feedback type with low impedance increases the number of elements and disadvantages the frequency characteristics. Performing base current compensation to reduce leakage current increases the number of elements and naturally limits the compensation ability. Ta.

The present invention aims to provide a lamp circuit that can eliminate the DC level difference caused by the clamp with a simple configuration even if the output impedance of the pre-stage circuit of the clamp capacitor is not small.

[Structure of the Invention (Means for Solving the Problems)] The clamp circuit of the present invention detects the emitter current of the first output limiter follower of the front-stage circuit of the clamp capacitor, and the clamp circuit is provided at a stage further preceding the first output limiter follower. The emitter current of the second emitter follower of opposite polarity is controlled.

(Function) By the means described above, the change in the voltage between the base and emitter of the first emitter follower, which is the origin of the DC step, can be canceled out by the change in the voltage between the base and emitter of the second emitter follower, so that the DC step can be eliminated. can.

(Example) Refer to the drawings below for an example of this invention! ! (Although this will be explained later, the same parts as in FIG. 5 are given the same reference numerals, and the different parts will be mainly explained in detail here.

FIG. 1 shows an embodiment of the present invention, in which transistor Q3
This differs from FIG. 5 in that a current mirror commercial is added.

That is, the input IN is connected to the base of the transistor Q3 whose collector is connected to the power supply VCC, and the emitter is connected to the base of the transistor Q2. transistor Q
The collector of transistor Q3 is connected to the input of current mirror CM, and the emitter of transistor Q3 is connected to the output of current mirror CM.

According to the above configuration, a current exactly equal to the current flowing through transistor Q2 flows through the emitter of transistor Q3 during the clamp period 18] and outside the clamp period, and a DC current of the same magnitude flows in the opposite direction to the DC step generated by transistor Q2 during clamping. Since the difference in level causes dirt, it can be offset.

I will explain in detail about zero killing (of DC step). Now, if the emitter current of transistor Q2 during the clamp period is Iep, and the emitter current outside the clamp period is ICP, then the potential difference VCP during the clamp period from the base of transistor Q3 to the emitter of transistor Q2 is VCP −V T −12n ( n-CP/I
53)-VT-nn(ICP/l52)-VT
−j2n −n(IS2/IS3),
The potential difference VCP outside the clamp period is VCP −V r
-12n (n I CP/ I 53) -VT -
An(ICP/l52) -VT-In-n(192/IS3).

Here, 182, IS3 are the respective saturation currents of transistors Q2 and Q3, VT is expressed as k T / q, and k
T is Boltzmann's constant, and q is the amount of charge. In addition, the human/output ratio of the current mirror CM was set to 1:n (n is a real number). Therefore, since the potential difference between the clamp period and the outside of the clamp period is completely equal, it is not affected by the amount of leakage current. In addition, in Fig. 1, the current source! The same effect can be obtained even if 2 is composed of a resistor.

2 and 3 show other embodiments of the present invention, in which a transistor Q12 is connected between the emitter of the transistor Q3 in FIG. 1 and the base of the transistor Q2.
It is equipped with a level shift circuit consisting of Qll,
Figure 3 shows the emitter of transistor Q3 and transistor Q.
between the bases of transistor Q21 and current source 121
A level shift circuit consisting of the following is provided.

Potential difference vcp during the clamp period from the base of transistor Q3 to the emitter of transistor Q2 in FIG.
is, VCP=Vy −fn (n・ICP/183)+V
r −J2n (n-ICP/l5I2)-VT −
nn(ICP/l5II)-VT-In(ICP
/ l52)=Vr −In (n”−ISII−1
92/IS3・l512), and the potential difference v outside the clamp period is ■(￥-VT-J2n (n・IC
P/l53)+VT-J2n (n-ICPnI
81)-VT-Jn(ICP/l5II)-VT-J2n(ICP/182)-VT-In
(n21811 182/l531S12). However, 1811 and l512 are the saturation currents of the transistors Qll and Q12.

From the base of transistor Q3 in Figure 3 to transistor Q
The potential difference VCP% VCP between the clamp period and outside the clamp period up to the emitter of No. 2 is obtained in the same way as in Figure 1, and also in Figure 3, there is no potential difference between the clamp period and outside the period, and there is no shift in the clamp level. .

[Effects of the Invention] As described in detail above, according to the clamp circuit of the present invention, even if the output impedance of the circuit before the clamp capacitor is not small, the DC step difference occurring in the output can be accurately canceled out, so that the clamp level can be reduced. There is no deviation, and accurate DC transmission is possible using the clamp circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing other embodiments of the invention, respectively, and FIGS. 4 and 5 are conventional circuit diagrams, respectively. The figure is shown below. Q1 to Q3...Transistor CM...Current mirror C1...
...Capacitor 11...Current source vl...Voltage source Toshiba Corporation

Claims (3)

[Claims] (1) A level shift circuit that shifts the level of an input signal, a first transistor whose base is supplied with the output of this level shift circuit, and a level of the level shift circuit that depends on the collector current of the first transistor. a current conversion circuit that outputs a current for controlling a shift amount;
A clamp capacitor connected between the emitter and the output of the transistor, and a clamp capacitor connected between the clamp capacitor and the output, and the charge of the clamp capacitor is set to a predetermined value so that the output becomes a predetermined value only during the clamp period. and a clamping means for holding the clamp circuit. (2) The level shift circuit is constituted by a second transistor, a signal is input to the base of the second transistor, and the emitter thereof is connected to the base of the first transistor. Clamp circuit described in item 1. (3) The clamp circuit according to claim 1, characterized in that a current source is connected to the emitter of the first transistor.