JPH0321076Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a two-phase clock signal generation circuit for generating two clock signals having a predetermined phase relationship.

[Background of the idea]

Conventionally, in digital signal processing circuits and the like, there are various types of circuits that divide one master clock signal at different frequency division ratios to obtain clock signals of different frequencies. If the master clock signal is simply divided by each frequency divider, the phases of the two clock signals will not have the specified relationship.
A circuit means is required to set the phases of two clock signals in a predetermined relationship, but all conventional circuits have drawbacks such as complicated circuits and the inability to easily adjust the phase relationship.

[Purpose of invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a two-phase clock signal generation circuit which eliminates the above-mentioned drawbacks of the conventional circuit and which is a simple circuit and can easily adjust the phase relationship between two clock signals.

[Structure of the idea]

A two-phase clock signal generation circuit according to the present invention includes: an oscillator that generates a master clock signal; first and second frequency dividers that receive the master clock signal as input and generate clock signals respectively;
a count value detector that detects that the frequency divider is at a predetermined count value and produces an output; and a count value detector that causes the output of the count value detector to stop the counting operation of the second frequency divider and the first frequency divider. and a frequency divider control circuit that releases the stoppage of the counting operation of the second frequency divider using a reference signal from the frequency divider.

Therefore, the counting operation of the second frequency divider is controlled according to the reference signal from the first frequency divider, and the counting operation of the second frequency divider is controlled according to the reference signal from the first frequency divider.
The two clock signals output from the and second frequency divider can have a predetermined phase relationship, and furthermore,
Although the circuit configuration is simple, it produces excellent effects such as being able to easily adjust the phase relationship between two clock signals by adjusting the count value detected by the count value detector.

〔Example〕

An embodiment of a two-phase clock signal generation circuit according to the present invention will be described below with reference to FIG. FIG. 1 is a block circuit diagram of an embodiment of the two-phase clock signal generating circuit of the present invention. In the figure, 1 is an oscillator that generates a master clock signal, and this master clock signal is input to a first frequency divider 2 and a second frequency divider 3, and is appropriately divided into the first and second frequency dividers. The signals are output to output terminals 4 and 5 as first and second clock signals, respectively. This first and second frequency divider 2, 3
Each of the counters is constructed by connecting a plurality of counters 6 and 7 in series. 8 is a count value detector that generates a detection output when the count value of the second frequency divider 3 reaches a predetermined value set in advance, and includes a detection output terminal 9 and a setting input terminal 10 for adjusting the set value.
and has. 11 is a frequency divider control circuit, which controls the second frequency divider 3 based on the detection output of the count value detector 8.
The counting operation of the second frequency divider 3 is stopped, and the stopping of the counting operation of the second frequency divider 3 is canceled at the rising or falling edge of the first clock signal generated at the first output terminal 4 of the first frequency divider 2. It is configured. Note that the frequency divider control circuit 11 is configured to receive only the first detection signal from the count value detector 8, and 12 is a reset terminal for resetting the frequency divider control circuit 11.

The two-phase clock signal generation circuit according to the present invention has the above-mentioned configuration and operates as follows. first,
A predetermined value is set in advance in the count value detector 8, and the frequency divider control circuit 11 is brought into a reset state. A master clock signal from the oscillator 1 is applied to the first and second frequency dividers 2, 3, and the first and second frequency dividers 2,
Counters 6 and 7 forming part 3 count sequentially. When the count value of the second frequency divider reaches a preset value, the detection output is applied from the count value detector 8 to the frequency divider control circuit 11, and from this frequency divider control circuit 11 the second frequency divider is applied. A signal for stopping the counting operation is applied to each counter 7 constituting the frequency divider 3, and the counting operation of the second frequency divider 3 is stopped. The counting operation of the first frequency divider 2 then proceeds and a first clock signal is generated. This first clock signal is applied to the frequency divider control circuit 11, and when the first clock signal rises or falls, the signal that stops the counting operation of the second frequency divider 3 is released, and the second The count operation of the frequency divider 3 is restarted. Thereafter, the first and second frequency dividers 2 and 3 divide the master clock signal of the oscillator 1 appropriately and output the first and second clock signals to the first and second output terminals 4 and 5, respectively. do.

Therefore, the second frequency divider 3 performs a counting operation based on the first clock signal of the first frequency divider 2, and divides the first clock signal and the second clock signal into a predetermined clock signal. It can be a phase relationship.

Furthermore, by appropriately adjusting the value preset in the count value detector 8, the phase relationship between the first and second clock signals can be adjusted as desired.

FIG. 2 is a detailed circuit diagram of another embodiment of the two-phase clock signal generation circuit according to the present invention. Second
In the figure, circuits with the same functions as in Figure 1 include the first
The same reference numerals as those in the drawings will be used, and redundant explanation will be omitted.
The first and second frequency dividers 2 and 3 are each composed of three counters 6 and 7, and the count value detector 13 is
The output terminals Q _A , Q _B , Q _C , Q _D of the three counters 7 constituting the second frequency divider 3 are connected to the input terminals of the NAND circuit 15 directly or via the inverter 14 as appropriate. This is what I did. Each output terminal Q _A , Q _B , of the counter 7 constituting the second frequency divider 3
Inverter 14 is connected between Q _C , Q _D and NAND circuit 15.
By intervening or not intervening,
The value preset in the counter value detector 13 can be easily adjusted, and the first and second frequency dividers 2,
The phase relationship between the first and second clock signals from 3 can be adjusted arbitrarily.

In the embodiment shown in FIG. 2, the detection signal of the count value detector 13 is supplied to the flip-flop 40 until the power supply voltage supplied to one input of the flip-flop 30 rises. When the power supply voltage rises, no subsequent detection signals are input to the flip-flop 40, and the counting operation of the counter 7 is not stopped.

FIG. 3 is a detailed circuit diagram of another embodiment of the two-phase clock signal generation circuit according to the present invention.
In Figure 3, circuits with the same functions as those in Figure 1 include:
The same reference numerals as in FIG. 1 are given, and redundant explanation will be omitted. The counter value detector 16 in FIG. 3 connects each output terminal of the counter 7 constituting the second frequency divider 3 to one input terminal of an exclusive OR circuit 17, and A voltage controlled by a count value setting switch 18 is applied to the input terminal, and the output terminal of each exclusive OR circuit 17 is connected to the input terminal of the NAND circuit 15. By operating the count value setting switch 18, the predetermined value can be easily adjusted as desired. Further, the frequency divider control circuit 19 is provided with a phase setting reset switch 20 so that the frequency divider control circuit 19 can be reset after arbitrarily setting a predetermined value of the count value detector 16. . Further, the reference signal from the first frequency divider 2 for canceling the stoppage of the counter operation of the second frequency divider 3 uses the output of each counter 6 constituting the first frequency divider 2 as a phase reference signal. It is configured to be switched by a signal changeover switch 21, so that the frequency of the clock that determines the phase relationship between the first and second clock signals can be selected.

In the embodiment shown in FIG. 3, the detection signal of the count value detector 16 is supplied to the flip-flop 40 until the power supply voltage supplied to one input of the flip-flop 30 rises. When the power supply voltage rises, no subsequent detection signals are input to the flip-flop 40, and the counting operation of the counter 7 is not stopped.

[Effect of idea]

According to the two-phase clock signal generation circuit according to the present invention, an oscillator that generates a master clock signal, first and second frequency dividers that each generate a clock signal by receiving the master clock signal as input, and the second a count value detector that detects that the frequency divider is at a predetermined count value and generates an output; and a count value detector that stops the counting operation of the second frequency divider based on the output of the count value detector; and a frequency divider control circuit that releases the stoppage of the counting operation of the second frequency divider using the reference signal from the frequency divider. The counting operation is controlled according to the reference signal, and two clock signals output from the first and second frequency dividers can be generated in a predetermined phase relationship,
Furthermore, by appropriately setting the count value detected by the count value detector, excellent effects such as being able to easily adjust the phase relationship between the two clock signals are achieved.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of one embodiment of the two-phase clock signal generation circuit of the present invention, FIG. 2 is a specific circuit diagram of another embodiment of the present invention, and FIG. FIG. 7 is a specific circuit diagram of another example. 1: Oscillator, 2: First frequency divider, 3: Second frequency divider, 8, 13, 16: Count value detector, 1
1, 19: Frequency divider control circuit.

Claims (1)

[Scope of utility model registration request] an oscillator that generates a master clock signal; first and second frequency dividers that receive the master clock signal as input and generate clock signals respectively; and detects that the second frequency divider is at a predetermined count value. a count value detector that generates an output, and an output of the count value detector within a predetermined time to stop the counting operation of the second frequency divider; 1. A two-phase clock signal generation circuit comprising: a frequency divider control circuit for canceling stoppage of counting operation of a frequency divider.