JPH03211644A - Control storage circuit for computing element - Google Patents

Abstract

PURPOSE:To prevent a data change in a control storage circuit so as to improve the reliability of data by repeating the reading operation and writing operation of data when an operation is not executed in a computing element. CONSTITUTION:When the operation is not executed in the computing element, a selection circuit 3 selects the output address signal 201 of a write address register 2, a control circuit 1 outputs '0' as a control signal 101, a control storage circuit 4 executes the read operation with the signal 201 as an address and output data 401 is stored in a read register 5 in an initial clock cycle. In a subsequent clock cycle, the selection circuit 3 selects the signal 201 again, the control circuit 1 outputs '1' as the control signal 101 and the control storage circuit 4 executes the write operation of output data 501 of the read register 5. At that time, an address signal 202 increased by one is stored in the write address register 2. Thus, the data change of the control storage circuit is prevented and the reliability of data is improved.

Description

TECHNICAL FIELD The present invention relates to a control storage circuit for an arithmetic unit, and more particularly to a control storage circuit for storing data for controlling an arithmetic unit used in an information processing device.

Prior Art Conventionally, in the control memory circuit of this type of arithmetic unit, control memory (RAM; Random Access M
elory) and read register,
While the arithmetic processing unit is in operation, only read operations are performed on the control memory.

In the control memory circuit of such a conventional arithmetic unit, only read operations are performed on the control memory while the arithmetic processing unit is operating, so the electric charge in the control memory decreases due to natural discharge and data corruption is likely to occur. This has the disadvantage that the reliability of the data decreases.

Purpose of the Invention The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and can make it difficult for data to become garbled.
An object of the present invention is to provide a control storage circuit for an arithmetic unit that can improve data reliability.

Structure of the Invention A control storage circuit for an arithmetic unit according to the present invention is a control storage circuit for an arithmetic unit that only performs an operation of reading data stored in a storage means when an arithmetic operation is executed by the arithmetic unit, reading means for sequentially reading out the data from the storage means when the arithmetic operation is not performed in the arithmetic unit; and data read by the reading means when the arithmetic operation is not performed in the arithmetic unit, to the storage means. The present invention is characterized by comprising a writing means for sequentially writing, and a suppressing means for suppressing sending of data read by the reading means to the arithmetic unit when the arithmetic operation is not executed in the arithmetic unit.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a control circuit 1 inputs an arithmetic execution instruction signal 100 that instructs an arithmetic unit (not shown) to execute an arithmetic operation, generates a control signal 101 according to the content of this arithmetic execution instruction signal 100, and writes it. Output to address register 2 and control storage circuit 4.

The write address register 2 sends its output address signal 201 to the adder 2 in response to the control signal 101 from the control circuit 1.
The address signal 202 incremented by "1" is stored in a.

The selection circuit 3 selects one of the read address signal 200 and the output address signal 201 from the write address register 2 according to the operation execution instruction signal 100, and supplies the selected address signal to the control storage circuit 4 as an output address signal 301. do.

The control storage circuit 4 receives the output address signal 3 from the selection circuit 3.
Control signal 10 from control circuit 1 with address 01
1, and the read data is output to the read register 5 as output data 401.

The read register 5 receives output data 4 from the control storage circuit 4.
01 is stored, and the output data 501 is stored in the control storage circuit 4.
output as write data and input data to the mask circuit 7.

A flip-flop (hereinafter referred to as FF) 6 holds an operation execution instruction signal 100 and outputs its output signal 601 to the mask circuit 7.

The mask circuit 7 performs mask processing on the output data 501 of the read register 5 in response to the output signal 6 (+1) from the FF 6, and sends the output data 701 to the arithmetic unit.

When the operation execution instruction signal 100 is 1", the control circuit 1 outputs "O" to the control signal 1 (11), and when the operation execution instruction signal 100 is "0', the control circuit 1 outputs "O" to the control signal 1 (11) in the first clock cycle. "0" is output to the control signal lO1 in the next clock cycle, and "0" is output to the control signal 101 in the next clock cycle.
” and “lo” are output sequentially.

Write address register 2 receives control signal 10 of control circuit 1
When 1 is 0, it enters a hold state and holds the stored value, and when the control signal 101 of the control circuit 1 is "1", the output address signal 201 is set to "1" by the adder 2a.
” Stores the incremented address signal 202.

The selection circuit 3 selects the output address signal 201 of the write address register 2 when the operation execution instruction signal 100 is "O", and selects the read address signal 200 when the operation execution instruction signal 100 is "1".

The control memory circuit 4 stores the control signal 101 of the control circuit 1 as “0”.
At this time, a read operation is performed using the output address signal 301 of the selection circuit 3 as an address, and the control signal 10 of the control circuit 1 is
1 is “1”, the output address signal 30 of the selection circuit 3
Read register 5 output data 50 using 1 as address
1 write operation is performed.

Since the mask circuit 7 does not perform mask processing on the output data 501 of the read register 5 when the output signal 601 of the FF6 is 1'', the output data 701, that is, the output data 501 of the read register 5 is used for calculation control in the arithmetic unit. I do.

On the other hand, in the mask circuit 7, the output signal 601 of the FF6 is "0".
Since the output data 501 of the read register 5 is masked at this time, no calculation is performed within the arithmetic unit.

First, when the operation execution instruction signal 100 is "1", that is, when the arithmetic unit is about to execute an operation, the selection circuit 3 selects the read address signal 200 and outputs it to the control storage circuit 4 as an output address signal 301. .

At this time, since the control circuit 1 outputs "0" as the control signal 1.01, the control storage circuit 4 performs a read operation using the read address signal 200 as an address, and the output data 401 is stored in the read register 5. .

The first node j, FF6 is set to “1” by the calculation execution instruction signal loo.
' is stored and the output signal 801 is output in the next clock cycle.
Since "1" is outputted to , the mask circuit 7 outputs the output data 501 of the read register 5 to the processor as output data 701 without performing any mask processing. Therefore, calculations are executed within the calculator.

Next, when the arithmetic execution instruction signal 100 is "0", that is, when the arithmetic unit does not execute an arithmetic operation, in the first clock cycle, the selection circuit 3 selects the write address register 2 from the write address register.
The output address signal 201 of “
0'' as the control signal 1.01, the control storage circuit 4 performs a read operation using the output address signal 201 of the write address register 2 as an address, and the output data 401 is read and stored in the register 5.

On the other hand, FF6 is set to “0” by the calculation execution instruction signal 100.
is stored. At this time, the write address register 2 enters a hold state because the control signal 101 of the control circuit 1 is "0".

In the next clock cycle, the selection circuit 3 selects the output address signal 201 of the write address register 2 again.
Since the control circuit 1 outputs "1" as the control signal 101, the control storage circuit 4 uses the output address signal 201 of the write address register 2 as an address and writes it into the read register 5.
Write operation of the output data 501 is performed.

That is, the data read from the control storage circuit 4 in the first clock cycle is written to the address of the control storage circuit 4 from which the data was read in the next clock cycle.

At this time, in the write address register 2, since the control signal 101 of the control circuit 1 is "1", the output address signal 201 is incremented by "1" to the address signal 20.
2 is stored.

As mentioned above, while the calculation execution instruction signal 100 is “0”,
A read operation from the control storage circuit 4 and a write operation in which data read by the read operation are written to the read address are repeatedly performed.

During this time, since "0" is stored in FF6, the mask circuit 7 performs mask processing on the output data 501 of the read register 5, and the sending of data to the arithmetic unit is suppressed. The operation is not executed.

In this way, when the arithmetic unit does not perform an operation, the control memory circuit 4 can be repeatedly read from the control memory circuit 4 and written to the address from which the read data has been read. Since the circuit 4 is charged by the write operation, data in the control storage circuit 4 is less likely to be garbled, and data reliability can be improved.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when no arithmetic operation is performed in the arithmetic unit, the operation of reading data from the control storage circuit and the write operation of writing the read data to the read address are repeated. By doing so, data garbled in the control storage circuit can be made less likely to occur, and data reliability can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1... Control circuit 5... Read register 2... Write address register 3...
...Selection circuit 7...Mask circuit 4...
...Control memory circuit

Claims (1)

[Claims] (1) A control storage circuit for an arithmetic unit that only performs an operation of reading data stored in a storage means when an arithmetic operation is executed by the arithmetic unit, and when the arithmetic operation is not executed by the arithmetic unit. reading means for sequentially reading the data from the storage means; writing means for sequentially writing the data read by the reading means into the storage means when the calculation operation is not executed in the calculation unit; A control storage circuit for an arithmetic unit, comprising a suppressing means for suppressing sending of data read by the reading means to the arithmetic unit when the arithmetic operation is not executed.