JPH03211652A - Direct memory access circuit - Google Patents

Abstract

PURPOSE:To attain high speed data transfer by incorporating counters in respective memory blocks and constituting an address circuit which independently generates addresses in respective blocks after a start address. CONSTITUTION:Respective memory blocks 6 incorporate the counters 7. When data transfer is started, data is read and written between the addresses concerned by writing the start address of a transfer source and a transfer destination in respective counters 7 at the time of transferring data between the memory blocks. The address is increased by one from the start address by transmitting a clock to respective counters 7, after data is transferred and data is read and written between subsequent addresses and so forth. Then, the clock generates the addresses subsequent to the start address in respective memory blocks 6 in the end. Thus, it is unnecessary to take a two-addresses-system for one data transfer, and data transfer is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a direct memory access circuit that transfers data between a plurality of memory blocks connected on a bus without using a processor.

Conventionally, in this type of direct memory access (DMA) circuit, DMA is used to transfer data between memory blocks.
The controller needs to address both the transfer source and transfer destination. Therefore, for example, [68000 DMA controller with three types of transfer modes] (magazine rNIKKEI ELECTRONIC51982, 8
, 2J, page 148), data transfer between memories is performed using a two-address method (double address mode) in which the DMA itself issues the transfer destination address and transfer source address twice. There is something I did.

Problem 2 to be Solved by the Invention The address method is used when the address line of the bus is 1
This is because there is only one set of data, but since one data transfer takes two bus cycles, the cycle time is long and the data transfer speed is slow.

Means for Solving the Problem In a direct memory access circuit that directly transfers data between multiple memory blocks connected on a bus through sequence control by a controller without going through a processor, a direct memory access circuit is connected to the address line of the bus. each memory block has a built-in counter that counts clocks from the controller, and a start address is written therein.
Each memory block was provided with an address circuit loaded with the count value of each counter.

Effect Each memory block has a built-in counter, and when transferring data between memory blocks, first write the start address of the transfer source and transfer destination to each counter, and then start the data transfer. Data is read and written between addresses. After data transfer, the address is incremented by 1 from the start address by sending a clock to each counter, and data is read and written between the next addresses. The process is the same thereafter, and in the end, the addresses after the start address in each memory block are generated by the clock, so there is no need to use a two-address method for one data transfer, and data transfer can be speeded up. . Here, the addresses are not limited to consecutive addresses; for example, by arbitrarily changing the number of clocks from the controller that drives the counter, even discontinuous addresses can be loaded.

Example An embodiment of the present invention will be described based on the drawings.

First, as shown in FIG. 2, the DM and A circuits of this embodiment connect to the CPU 2 and the DMA controller (DMAC
) 3 and, for example, two 1.2-th memory blocks 4 and 5.

Here, regarding one memory block, for example, the first memory block 4, as shown in FIG. 1, the address input of the memory 6 connected to the data line ID in the bus 1,
An address circuit 8 with a counter 7 interposed between it and the address line IA on the bus l is formed. The counter 7 has a loading function, and loads the address of the memory 6 based on its count value. The counter 7 is
The clock terminal is connected to the PU 2 to write the start address, and the clock terminal is connected to the DMAC 5 to input the clock to be counted.

The same applies to the second memory block 5 side.

In such a configuration, for example, the first memory block 4
The operation of continuously transferring data from the first memory block to the second memory block 5 will be explained with reference to FIG. First, CPU2
writes the number of data words to be transferred to DMAC5. at the same time,
The start address of the transfer source is written in the counter 7 in the first memory block 4, and the start address of the transfer destination is written in the counter 7 in the second memory block 5. Next, the CPU
2 sends a DMA operation command to the DMAC 5.

In response, the DMAC 5 outputs a read signal to the first memory block 4 and a write signal to the second memory block 5, thereby writing the data read from the start address of the first memory block 4. is written to the starting address in the memory 6 in the second memory block 5 through the data line ID on the bus 1. Next, when the DMAC 5 outputs a clock to each counter 7, the start address is changed to an address incremented by 1, and data is read and written between these addresses. Subsequent data transfers are performed in the same manner. Therefore, the DMAC 3 only needs to sequentially output clocks to update and generate addresses.

By the way, if the clock sent by the DMAC 5 to each counter 7 is not fixed to 1 clock but is set to a plurality of arbitrary clocks, discontinuous addresses can be loaded. For example, as shown in FIG. 4, after one word of data is transferred between each start address, if two clocks are sent to the counter 7 in the second memory block 5 as the transfer destination, This means that the address two addresses ahead is specified, and writing can be performed to this address, making it possible to correspond to any address.

Effects of the Invention In the present invention, as described above, each memory block has a built-in counter and an address circuit is configured to independently generate addresses in each block after the start address.
There is no need to use a 2-address method when transferring data between memory blocks, clock control by the controller is sufficient, high-speed data transfer is possible, and in particular,
It has the flexibility to load even discontinuous addresses by controlling the number of clocks.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention, and Fig. 1 is a block diagram of the main parts, Fig. 2 is a block diagram showing the overall configuration, and Fig. 3 is a block diagram showing the overall configuration.
The figure is an explanatory diagram showing DMA operation using continuous addresses.
The figure is an explanatory diagram showing a DMA operation using discontinuous addresses. 1...Bus, IA...Address line, 3...Controller, 4.5...Memory block, 7...Counter, 8...Address circuit 3'' Figure 37'', 3 figure mark 1 Atsushi lll figure

Claims (1)

[Claims] 1. In a direct memory access circuit that directly performs data transfer between a plurality of memory blocks connected on a bus under sequence control by a controller without going through a processor, Each memory block has a built-in counter in which a start address is written and counts clocks from the controller, and each memory block is provided with an address circuit that is loaded by the count value of each counter. Direct memory access circuit. 2. The direct memory access circuit according to claim 1, wherein discontinuous addresses are loaded depending on the number of clocks from a controller that drives the counter.