JPH03211836A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03211836A JPH03211836A JP745590A JP745590A JPH03211836A JP H03211836 A JPH03211836 A JP H03211836A JP 745590 A JP745590 A JP 745590A JP 745590 A JP745590 A JP 745590A JP H03211836 A JPH03211836 A JP H03211836A
- Authority
- JP
- Japan
- Prior art keywords
- film
- tungsten silicide
- melting point
- polycrystalline silicon
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 238000002844 melting Methods 0.000 claims abstract description 12
- 230000008018 melting Effects 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 10
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000006244 Medium Thermal Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法、とくに信頼性の高い
半導体素子の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a highly reliable semiconductor element.
従来の技術
近年、半導体素子の微細化や高速化に伴い、多結晶シリ
コンと高融点金属の２層構造の配線、いわゆるポリサイ
ド配線が広く使用されるようになってきた。BACKGROUND OF THE INVENTION In recent years, with the miniaturization and speeding up of semiconductor devices, so-called polycide wiring, which has a two-layer structure of polycrystalline silicon and high melting point metal, has come into widespread use.
以下、従来の半導体装置の製造方法を第２図を用いて説
明する。A conventional method for manufacturing a semiconductor device will be described below with reference to FIG.
第２図（ａ）において、半導体基板上の熱酸化膜などに
よる段差部２上にＢＰＳＧなどの酸化膜３を被着する。In FIG. 2(a), an oxide film 3 such as BPSG is deposited on a stepped portion 2 formed by a thermal oxide film or the like on a semiconductor substrate.
次に第２図（ｂ）において、酸化膜３上に多結晶シリコ
ン膜４を１５００Ａ程度被着させる。その後、第２図（
Ｃ）において、多結晶シリコン膜４上から、熱拡散法に
より、燐６を多結晶シリコン膜４中に拡散する。その後
、第２図（ｄ）においてタングステンシリサイド膜５を
ＣＶＤ法などにより２５００Ａ程度堆積させる。その後
、ホトレジストをマスクとして、ポリサイド配線を形成
する。Next, in FIG. 2(b), a polycrystalline silicon film 4 of about 1500 Å is deposited on the oxide film 3. After that, see Figure 2 (
In C), phosphorus 6 is diffused into the polycrystalline silicon film 4 from above the polycrystalline silicon film 4 by a thermal diffusion method. Thereafter, as shown in FIG. 2(d), a tungsten silicide film 5 of about 2500 Å is deposited by CVD or the like. Thereafter, polycide wiring is formed using photoresist as a mask.
発明が解決しようとする課題
従来の技術では、第２図（Ｃ）に示すように多結晶シリ
コン膜４上から燐６を熱拡散するときに、熱により多結
晶シリコン膜４の下の酸化膜３（ＢＰＳＧ）が流れ、段
差部２で、酸化膜３と多結晶シリコン４がオーバーハン
グ状になり、その上に堆積するタングステンシリサイド
膜５等の高融点金属膜もオーバーハング状になる。この
ため、その後ホトレジストによりパターンニングする際
、オーバーハング状の部分で配線が短絡する。Problems to be Solved by the Invention In the conventional technology, when phosphorus 6 is thermally diffused from above the polycrystalline silicon film 4 as shown in FIG. 2(C), the oxide film under the polycrystalline silicon film 4 is 3 (BPSG) flows, and the oxide film 3 and polycrystalline silicon 4 form an overhang at the stepped portion 2, and the high melting point metal film such as the tungsten silicide film 5 deposited thereon also forms an overhang. For this reason, when patterning is subsequently performed using photoresist, the wiring is short-circuited at the overhanging portion.
課題を解決するための手段
本発明の半導体装置の製造方法は、燐等の不純物を熱拡
散する代わりに、高融点金属膜もしくはそのシリサイド
膜上から、不純物をイオン注入法により注入する工程を
備えている。Means for Solving the Problems The method for manufacturing a semiconductor device of the present invention includes a step of implanting impurities from a high melting point metal film or its silicide film by ion implantation instead of thermally diffusing impurities such as phosphorus. ing.
作用
このようにすれば、ポリサイド配線下の酸化膜は流れな
くなり、オーバーハングも形成されない。したがってレ
ジストパターンにより配線を形成する際の短絡もなくな
る。By doing this, the oxide film under the polycide wiring will not flow and no overhang will be formed. Therefore, there is no short circuit when wiring is formed using a resist pattern.
実施例
以下、本発明の一実施例を図面を参照しなから説明する
。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図（ａ）において、半導体基板１上に熱酸化膜など
により段差部２が形成される。その上にＢＰＳＧ３など
酸化膜を形成する。次に第１図（ｂ）において、多結晶
シリコン膜４を約１５００Ａ程度形成し、第１図（Ｃ）
においてタングステンシリサイド膜５を２５００Ａ程度
形成する。その後、第１図（ｄ）において、タングステ
ンシリサイド膜５上より、燐をイオン注入法により注入
する。その後レジストパターンによりポリサイド配線を
形成する。In FIG. 1(a), a step portion 2 is formed on a semiconductor substrate 1 using a thermal oxide film or the like. An oxide film such as BPSG3 is formed thereon. Next, in FIG. 1(b), a polycrystalline silicon film 4 of about 1500 Å is formed, and as shown in FIG.
Then, a tungsten silicide film 5 of about 2500 Å is formed. Thereafter, as shown in FIG. 1(d), phosphorus is implanted onto the tungsten silicide film 5 by ion implantation. Thereafter, polycide wiring is formed using a resist pattern.
なお、本実施例では、高融点金属膜をタングステンシリ
サイド膜としたが、その他の高融点金属もしくはそのシ
リコン化合物でも同様な効果が期待できる。In this embodiment, a tungsten silicide film is used as the high melting point metal film, but similar effects can be expected with other high melting point metals or their silicon compounds.
発明の効果
以上のように、本発明によれは、タングステンシリサイ
ドなどの高融点金属膜上より、不純物をイオン注入法で
注入することにより、酸化膜、他結晶シリコン膜、高融
点金属膜もしくはシリサイド膜の段差部でのオーバーハ
ングがなくなり、ドライエッチのとき、エツチング残り
が発生せず、信頼性の高いポリサイド配線を形成できる
。Effects of the Invention As described above, according to the present invention, an oxide film, a polycrystalline silicon film, a high melting point metal film, or a silicide film is formed by implanting impurities onto a high melting point metal film such as tungsten silicide using an ion implantation method. There is no overhang at the step portion of the film, no etching residue is generated during dry etching, and highly reliable polycide wiring can be formed.
第１図は本発明の一実施例における半導体装置の製造方
法を示す工程断面図、第２図は従来例を説明するための
工程断面図である。
１・・・・・・半導体基板、２・・・中熱酸化膜などに
よる段差部、３・・・・・・酸化膜、４・・・・・・他
結晶シリコン膜、５・・・・・・タングステンシリサイ
ド膜、６・・・・・・燐。FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process sectional view for explaining a conventional example. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...Stepped portion by medium thermal oxide film, etc., 3...Oxide film, 4...Other crystal silicon film, 5... ...Tungsten silicide film, 6...Phosphorus.
Claims (1)
上記多結晶シリコン膜上に高融点金属膜もしくはそのシ
リサイド膜を堆積する工程と、上記高融点金属膜もしく
はそのシリサイド膜上から不純物をイオン注入法により
注入する工程と、ホトレジストをマスクとして前記多結
晶シリコン膜と前記高融点金属膜もしくはそのシリサイ
ド膜をエッチングする工程とをそなえたことを特徴とす
る半導体装置の製造方法。a step of depositing a polycrystalline silicon film on the semiconductor substrate;
A step of depositing a high melting point metal film or its silicide film on the polycrystalline silicon film, a step of implanting impurities from above the high melting point metal film or its silicide film by ion implantation, and a step of depositing the high melting point metal film or its silicide film on the polycrystalline silicon film; A method for manufacturing a semiconductor device, comprising a step of etching a silicon film and the high melting point metal film or its silicide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP745590A JPH03211836A (en) | 1990-01-17 | 1990-01-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP745590A JPH03211836A (en) | 1990-01-17 | 1990-01-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03211836A true JPH03211836A (en) | 1991-09-17 |
Family
ID=11666301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP745590A Pending JPH03211836A (en) | 1990-01-17 | 1990-01-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03211836A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100322523B1 (en) * | 1995-02-22 | 2002-06-20 | 윤종용 | Method for planarizing semiconductor device with capping layer |
-
1990
- 1990-01-17 JP JP745590A patent/JPH03211836A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100322523B1 (en) * | 1995-02-22 | 2002-06-20 | 윤종용 | Method for planarizing semiconductor device with capping layer |
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