JPH03217123A - Phase locked loop circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase-locked circuit, and particularly to a loop filter.

[Conventional technology] FIG. 2 is a block diagram showing a conventional phase synchronization circuit.

In the figure, 1 is a phase comparator that detects phase errors, 2 is a loop filter, 3 is a voltage controlled oscillator, 4 is an input signal, and 5
is an output signal, 6 is a phase error signal, and 7 is an oscillation control signal.

In FIG. 2, a phase error is detected between an input signal 4 and an output signal 5, and a phase error signal 6 is output.

The phase error signal 6 is converted into an oscillation control signal 7 by the loop filter 2. The output signal 5 is input to the phase comparator 1, and this circuit is locked when the phases of the input signal 4 and the output signal 5 match.

[Problem to be solved by the invention] By the way, in a conventional phase-locked circuit, when an input signal is no longer input, the phase comparator detects a phase lag, and as a result, the oscillation control signal slows down the frequency of the voltage-controlled oscillator. do. If an input signal is input in this state,
Since frequency synchronization must be performed as well as phase synchronization, there is a problem in that it takes time to perform read-in.

SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a phase-locked circuit that can quickly lock-in.

[! 11111] The phase synchronized circuit of the present invention includes: a signal input detection circuit that detects whether the next input signal is input within a certain period of time after the input signal is input; and the signal input detection circuit. comprises a selection circuit that selects either the input signal or the reference clock signal according to the output signal of the
A detection result of detecting a phase error between the output signal of the selection circuit and the output signal of the voltage controlled oscillator is input to a loop filter, and the oscillation of the voltage controlled oscillator is controlled by the loop filter.

[Example] Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 shows a phase locked circuit in one embodiment of the present invention. In the figure, the same parts as in FIG. 2 are given the same reference numerals. Further, 8 is a reference clock signal, 9 is a selection circuit that selects either the input signal 4 or the reference clock 8, 10 is a signal input detection circuit that detects whether the input signal 4 is input within a certain period of time, and 11 is a signal This is a switching signal that switches the output of the selection circuit 9 based on the output of the input detection circuit 10.

Suppose now that the input signal 4 is input at a time interval shorter than the time set by the signal input detection circuit 10. The signal input detection circuit 10 detects that the signal is input manually,
The output of the selection circuit 9 is switched to the input signal 4 by the switching signal 11.
is output. Therefore, in the phase comparator 1, the input signal 4 and the output signal 5 are phase-compared and locked when the phases match.

Next, assume that the input signal 4 is no longer input from the above state. The signal input detection circuit 10 detects that no signal is input for a certain period of time, and the output of the selection circuit 9 is switched from the input signal 4 to the reference clock 8 by a switching signal 11. Therefore, in the phase comparator 1, the reference clock 8 and the output signal 5 are compared in phase and locked when the phases match.

Next, assume that input signal 4 is input again from the above state. The signal input detection circuit 10 detects that a signal is input, and the output of the selection circuit 9 is switched to the input signal 4 by the switching signal 11. Therefore, in the phase comparator 1, the input signal 4 and the output signal 5 are phase-compared and locked when the phases match.

Here, the clock frequency of the reference clock 8 is set to the input signal 4.
If the frequency is set to be the same as the frequency of , when the input signal 4 is input again, there is no need for frequency synchronization and only phase synchronization is required. Therefore, the time required for lock-in is short and lock-in can be achieved quickly.

[Effects of the Invention] As described above, according to the present invention, when no input signal is input, the phase synchronized circuit is synchronized with the reference clock, so when the input signal is input again, it is quickly locked. It has the effect of being able to be read in.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram of a conventional phase-locked circuit. 1... Phase comparator 2...Loop filter 3...Voltage controlled oscillator 4...Input signal 5... Output signal 6...Phase error signal 7...Oscillation control signal 8...Reference clock 9...Selection circuit 10...Signal input detection circuit 11...Switching signal that's all

Claims (1)

[Claims] A signal input detection circuit that detects whether a next input signal is input within a certain time after the input signal is input, and selects either the input signal or the reference clock signal based on the output signal of the signal input detection circuit. Equipped with a selection circuit to
A phase locked circuit characterized in that a detection result of detecting a phase error between the output signal of the selection circuit and the output signal of the voltage controlled oscillator is input to a loop filter, and the loop filter controls oscillation of the voltage controlled oscillator.