JPH0321842U - - Google Patents

Info

Publication number
JPH0321842U
JPH0321842U JP8219489U JP8219489U JPH0321842U JP H0321842 U JPH0321842 U JP H0321842U JP 8219489 U JP8219489 U JP 8219489U JP 8219489 U JP8219489 U JP 8219489U JP H0321842 U JPH0321842 U JP H0321842U
Authority
JP
Japan
Prior art keywords
chip
wafer
chips
projection exposure
alignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8219489U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8219489U priority Critical patent/JPH0321842U/ja
Publication of JPH0321842U publication Critical patent/JPH0321842U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本案の実施例に用いた縮小投影露光装
置の全体図、第2図はこの処理を行うための概略
フローチヤート図である。 1…X−Yステージ、2…縮小レンズ、3…レ
テイクル、4…ウエハ、5…パターン検出器、6
…データ処理装置。
FIG. 1 is an overall view of a reduction projection exposure apparatus used in an embodiment of the present invention, and FIG. 2 is a schematic flowchart for carrying out this process. 1...X-Y stage, 2...reducing lens, 3...reticle, 4...wafer, 5...pattern detector, 6
...Data processing equipment.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 縮小レンズとパターン検出光学系と位置計測装
置(レーザ測長系)、パターン検出データの処理
装置より成る縮小投影露光装置において、回路パ
ターンが描画されているレテイクルと、ウエハ上
のチツプを交互にパターン検出を行い重ね合わせ
露光するチツプアライメント方式で、チツプアラ
イメントが不可能なチツプに対しても疑似的にチ
ツプアライメントを行うことによつて、ウエハ上
の全てのチツプに対して高精度なアライメントを
行うことを特徴とする縮小投影露光装置。
In a reduction projection exposure system consisting of a reduction lens, a pattern detection optical system, a position measurement device (laser length measurement system), and a processing device for pattern detection data, the reticle on which the circuit pattern is drawn and the chip on the wafer are patterned alternately. A chip alignment method that performs detection and overlapping exposure performs pseudo chip alignment even for chips for which chip alignment is not possible, achieving highly accurate alignment for all chips on the wafer. A reduction projection exposure apparatus characterized by:
JP8219489U 1989-07-14 1989-07-14 Pending JPH0321842U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8219489U JPH0321842U (en) 1989-07-14 1989-07-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8219489U JPH0321842U (en) 1989-07-14 1989-07-14

Publications (1)

Publication Number Publication Date
JPH0321842U true JPH0321842U (en) 1991-03-05

Family

ID=31628786

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8219489U Pending JPH0321842U (en) 1989-07-14 1989-07-14

Country Status (1)

Country Link
JP (1) JPH0321842U (en)

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