JPH03219631A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03219631A JPH03219631A JP1410890A JP1410890A JPH03219631A JP H03219631 A JPH03219631 A JP H03219631A JP 1410890 A JP1410890 A JP 1410890A JP 1410890 A JP1410890 A JP 1410890A JP H03219631 A JPH03219631 A JP H03219631A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- resist
- insulating film
- semiconductor device
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000005530 etching Methods 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
[産業上の利用分野1
本発明は、半導体装置の製造方法、特に絶allIにテ
ーパーを付けるエツチング方法に関するものである。
[発明の概要1
本発明は、絶縁膜のエツチング方法において、絶!1l
ll上にレジストで、レジストと半導体主表面との接触
角が90度以下のパターンを形成し、絶ttt+iとレ
ジストの選択比が3以下のエツチングにより、絶縁膜を
途中までエツチングし、その後、ウェットエツチングに
より、絶縁膜を最終までエツチングする工程とすること
により、テーパーの付いたエツチングホール(以下コン
タクトと称す)を形成し、さらには、その後に形成され
る例えば配線電極のコンタクト部分でのつき回りをよく
するものである。
[従来の技術l
従来のコンタクト部分の形成方法としては1例えば絶縁
膜をドライエツチングで行なった場合、第2図のように
、コンタクト部分にテーパーはつかず、その後に配線さ
れる配線電極の配線部分のつき回りも、余りよくなかっ
た。
〔発明が解決しようとする課題l
従来のコンタクト部分の配線電極のつき回りは余りよく
なく、これを改善するために例えば、第3図のようにB
PSGを用いたりフロー技術が用いられたりしている。
ただし、仮にリフロー技術を用いてもコンタクト上部の
角度(304)は改善されるものの、半導体表面との接
触角(305)は余り改善されず、結果として配線電極
のつき回りはよくならない、そこで本発明はこのような
課題を解決するもので、その目的とする所は。
コンタクト部分にテーパーを付けることにより、結果と
して配線電極のつき回りの良いコンタクト部分のエツチ
ングの形成方法を提供する所にある。
[課題を解決するための手段]
本発明の半導体装置の形成方法は、絶縁謹上にレジスト
で、レジストと半導体主表面との接触角が90度以下の
所定のパターンを形成する工程と、絶縁膜とレジストの
選択比が小さいエツチングにより、絶a++*を途中ま
でエツチングする工程と、その後、ウェットエツチング
により、絶縁膜な最終までエツチングする工程としたこ
とを特徴とする。[Industrial Application Field 1] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an etching method for tapering an absolutely all I semiconductor device. [Summary of the Invention 1 The present invention provides an excellent method for etching an insulating film. 1l
A resist pattern is formed on the ll with a contact angle of 90 degrees or less between the resist and the main surface of the semiconductor, and the insulating film is etched halfway by etching with absolute ttt+i and a resist selectivity of 3 or less, and then wet etching is performed. By etching the insulating film to the final stage, a tapered etching hole (hereinafter referred to as a contact) is formed, and furthermore, it is possible to form a tapered etching hole (hereinafter referred to as a contact), and furthermore, it is possible to form a tapered etching hole (hereinafter referred to as a contact). It is something that makes things better. [Conventional Techniques] Conventional methods for forming contact portions are 1. For example, when an insulating film is dry etched, the contact portion is not tapered as shown in Fig. 2, and the wiring of the wiring electrode to be wired afterwards is The fit of the parts was also not very good. [Problems to be Solved by the Invention 1] The coverage of the wiring electrode in the conventional contact part is not very good, and in order to improve this, for example, as shown in Fig. 3,
PSG or flow technology is used. However, even if reflow technology were used, although the angle (304) of the upper part of the contact would be improved, the contact angle (305) with the semiconductor surface would not be much improved, and as a result, the coverage of the wiring electrode would not be improved. The invention is intended to solve these problems, and what is its purpose? The object of the present invention is to provide a method of etching a contact portion that provides good coverage of the wiring electrode by tapering the contact portion. [Means for Solving the Problems] A method for forming a semiconductor device of the present invention includes a step of forming a predetermined pattern with a resist in which the contact angle between the resist and the main surface of the semiconductor is 90 degrees or less, and forming an insulating film. The method is characterized by a step of etching the absolute a++* partway through etching with a low selectivity of the resist and a resist, and then a step of etching the insulating film to the final stage by wet etching.
第1図は1本発明の半導体装置の一実施例に於ける主要
工程図である。以下、第1図に従い1本発明の半導体装
置の製造方法を説明する。
(第1図(a))(101)は基板となる例えばSi基
板である。(102)は基板の主表面上に形成された絶
縁膜であり1例えば5i02を例えば5000A形成す
る。(103)はレジストであり、(102)の上に例
えば10000Aの厚さで形成する。そしてその形状は
(102)との接触角を小さくするために、パターンを
形成後、熱(例えば150℃、30分)を加える。
(第1図(b))次に絶nlIとレジストとの選択比(
=絶縁膜のエツチング速度/レジストのエツチング速度
)の小さなエツチング、例えばスパッタエツチングなど
で、エツチングを行なう0選択比が小さいため、レジス
トの形状がそのまま、絶iil!Iのエツチング形状と
な−る。ただし、逆にいってSi基板上でエツチングが
終了したのが確認出来ないため、本発明では、絶縁膜の
途中までエツチングする。
(第1図(C))次に例えば)IFとNH4Fの混酸で
、ウェットエツチングを行なう、ウェットエツチングは
等方的なエツチングであるため、スパッタエツチングで
のテーパーの付いた形状はそのまま保持され、かつエツ
チングはSi表面でストップする。
このようにして、テーパーのついたコンタクト部分のエ
ツチング形状を得る。
また、エツチングの形状はレジストのパターン形状によ
るため、レジストのパターン形状をコントロールするこ
とにより任意のエツチング形状が選られる。
【発明の効果J
以上述べてきた様に、本発明によれば、半導体装置の製
造方法において、絶縁謹上にレジストで、レジストと半
導体主表面との接触角が90度以下の所定のパターンを
形成する工程と、絶縁膜とレジストの選択比が3以下の
エツチングにより、前記絶n、l11を途中までエツチ
ングする工程と、その後、ウェットエツチングにより、
絶縁膜を最終までエツチングする工程とを強誘電体膜を
形成する工程としたため、テーパーの付いたエツチング
が可能となり、さらには、その後1こ形成される配線電
極のコンタクト部分での、つき回りがよ(なるという効
果を有する。FIG. 1 is a diagram showing the main steps in one embodiment of the semiconductor device of the present invention. Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be explained with reference to FIG. (FIG. 1(a)) (101) is a substrate, for example, a Si substrate. (102) is an insulating film formed on the main surface of the substrate, and is formed with 1, for example, 5i02 of, for example, 5000A. (103) is a resist, which is formed on (102) to a thickness of, for example, 10,000 Å. In order to reduce the contact angle with (102), heat (for example, 150° C., 30 minutes) is applied after forming the pattern. (Figure 1(b)) Next, selectivity ratio between absolute nlI and resist (
= Etching speed of insulating film / Etching speed of resist) is a small etching, such as sputter etching, and since the etching selectivity is small, the shape of the resist remains unchanged! It becomes the etched shape of I. However, since it is not possible to confirm that the etching has been completed on the Si substrate, in the present invention, etching is performed halfway through the insulating film. (Fig. 1 (C)) Next, wet etching is performed using a mixed acid of IF and NH4F. Since wet etching is isotropic etching, the tapered shape of sputter etching is maintained as it is. Moreover, etching stops at the Si surface. In this way, the etched shape of the tapered contact portion is obtained. Furthermore, since the etching shape depends on the resist pattern shape, any etching shape can be selected by controlling the resist pattern shape. Effects of the Invention J As described above, according to the present invention, in the method of manufacturing a semiconductor device, a predetermined pattern is formed with a resist in order to ensure insulation, and the contact angle between the resist and the main surface of the semiconductor is 90 degrees or less. a step of etching the insulating film and resist to the middle by etching with a selectivity ratio of 3 or less, and then a step of etching the insulating film to the resist to the middle, and then wet etching,
Since the process of etching the insulating film to the final stage is combined with the process of forming the ferroelectric film, it is possible to perform tapered etching, and furthermore, the coverage at the contact part of the wiring electrode that is formed after that is reduced. It has the effect of becoming.
第1図(a)〜(c)は本発明の半導体装置の製造方法
の主要工程図であり、第2図、第3図は従来のコンタク
ト部分の断面図である。
(101) ・ ・ ・ ・ ・
(102) ・ ・ ・ ・ ・
(103) ・ ・ ・ ・ ・
(203) (303)
(304) ・ ・ ・ ・ ・
・Si基板
・絶縁膜
・レジスト
・配線電極
・コンタクト上部の角度
(305)
コンタクトの半導体表
面との接触角
以
上FIGS. 1(a) to 1(c) are main process diagrams of the method of manufacturing a semiconductor device of the present invention, and FIGS. 2 and 3 are sectional views of a conventional contact portion. (101) ・ ・ ・ ・ ・ (102) ・ ・ ・ ・ ・ (103) ・ ・ ・ ・ ・ (203) (303) (304) ・ ・ ・ ・ ・ ・Si substrate, insulating film, resist, wiring electrode, Angle at the top of the contact (305) Greater than the contact angle with the semiconductor surface of the contact
Claims (1)
絶縁膜上にレジストで、レジストと半導体主表面との接
触角が90度以下の所定のパターンを形成する工程と、 前記絶縁績とレジストの選択比が3以下のエッチングに
より、前記絶縁績を途中までエッチングする工程と、そ
の後、ウェットエッチングにより、前記絶縁膜を最終ま
でエッチングする工程とを 含むことを特徴とする半導体装置の製造方法。(1) a step of forming an insulating film on the main surface of the semiconductor; a step of forming a predetermined pattern with a resist on the insulating film in which the contact angle between the resist and the main surface of the semiconductor is 90 degrees or less; and the insulating film. manufacturing a semiconductor device, comprising the steps of: etching the insulation film halfway through etching with a resist selectivity of 3 or less; and then etching the insulation film to the end through wet etching. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1410890A JPH03219631A (en) | 1990-01-24 | 1990-01-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1410890A JPH03219631A (en) | 1990-01-24 | 1990-01-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03219631A true JPH03219631A (en) | 1991-09-27 |
Family
ID=11851925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1410890A Pending JPH03219631A (en) | 1990-01-24 | 1990-01-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03219631A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593179B2 (en) * | 1999-11-18 | 2003-07-15 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device |
-
1990
- 1990-01-24 JP JP1410890A patent/JPH03219631A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593179B2 (en) * | 1999-11-18 | 2003-07-15 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device |
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