JPH03224042A - Access controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a memory access control device, and more particularly, to control of the difference in access time between a CPU and a memory.

<Conventional technology> When accessing memory with a CPU, if the memory access time is slower than the CPU access time, the CPU bus cycle is extended by one clock so that data can be read and written even from low-speed memory. It is being controlled to the extent possible. The time expansion in clock units of the bus cycle is determined by the number of expansion clocks, such as 0 for no wait, 1 clock for 1 way l~, and 2 clocks for 2 waits. being called.

FIG. 2 is a block diagram showing an example of such a conventional control circuit. The address decoder 1 decodes the input address ADH into an expansion time selection signal for a bus cycle assigned to each address area, and outputs the signal. In the figure, the expansion time selection signal WO1 has an expansion time of 0 depending on the address ADH, the expansion time selection signal Wl/W2 has an expansion time of 1 or 2 clocks, and the expansion time selection signal Wl/W2 has an expansion time of 3 clocks.
An example is shown in which one of the expansion time selection signals W3 serving as a clock is output. The expansion time selection signal WO is output to the OR gate 2 and is applied to the chip select terminal of the first memory 4 via the inverter 3, and the expansion time selection signals Wl and /W2 are applied to the AND gates 5 and 6 as gate control signals. At the same time as being outputted, the second
The expansion time selection No. 18 W3 is output as a wait time signal to the AND gate 9 and is also applied to the chip select terminal of the third memory 11 via the inverter 10. In addition, since two types of memories with different wait times are selectively mounted as the second memory 8, they are removably attached (hanged) via sockets. Clock CL added
The wait time signals WTI to WT3 expanded in units of K are output to AND gates 5 and 6.9. That is, +5■ is applied to the data terminal of the D-type flip-flop 12, the clock CLK from the CPU is applied to the clock terminal, and the address latch enable signal ALE is applied from the CPU to the clear terminal CLR. The terminal output is applied to the data terminal of the D-type flip-flop 13 and also to the AND gate 5. A clock CLK is applied from the CPU to the clock terminal of the D-type flip-flop 13, and an address latch enable signal ALE is applied from the CPU to the clear terminal CLR.
The Q terminal output is applied to the data terminal of the D-type flip-flop 14 and also to the AND gate 6. The clock terminal of the D-type flip-flop 14 is connected to the CPU.
A clock CLK is applied to the clear terminal CLR, an address latch enable signal ALE is applied from the CPU to the clear terminal CLR, and the Q terminal output is applied to the AND gate 9. The output signal of AND gates 5 and 6 is the changeover switch 1
5 to the OR gate 2, and the output signal of the AND gate 9 is directly applied to the OR gate 2. Then, the output signal of OR gate 2 is C as a ready signal RDY.
Added to PU.

FIG. 3 is a timing chart explaining the operation of FIG. 2, and shows an example in which the bus cycle is two clocks. C
The PU inputs a clock CLK as shown in (a) to the clock terminals of the flip-flops 12 to 14, respectively. C
Address AD added from PU to address decoder 1
H changes as shown in (b). Further, the CPU sends an address latch enable signal ALE shown in FIG.
On the other hand, a ready signal RDY as shown in (d) is applied to the CPU from the OR gate 2.

The CPU always monitors the ready signal RDY, and if it is not in the ready state, it extends the bus cycle by one clock. Here, the ready signal RDY is applied to the memories 4 and 8 connected to each address area of the address decoder 1.
．． 11 are generated for each period. That is, for the address ADR of the address area assigned to the memory 4, a period equal to a bus cycle (two clocks) is generated. For the address ADR of the address area assigned to memory 8, if the memory to be implemented is 1-wait, selector switch 1 is selected.
5 selects the output signal of AND gate 5 to generate a wait time signal that is 61 clocks longer than the bus cycle, and when the mounted memory is 2-wait, selector switch 15 selects the output signal of AND gate 6. A wait time signal that is 62 clocks longer than the bus cycle is generated. Furthermore, a wait time signal that is three clocks longer than the bus cycle is generated for the address ADH of the address area assigned to memory 1.

These wait time signals are outputted to the CPU via the OR gate 2 as a ready signal RDY.

<Problems to be Solved by the Invention> However, according to such a conventional configuration, either a 1-wait or 2-wait memory is implemented for the address ADR of the address area allocated to the memory 8. Therefore, in order to selectively generate a predetermined ready signal RDY according to the memory to be mounted, a changeover switch 15 is provided and the changeover switch 15 must be manually operated, resulting in poor operability.

The present invention has focused on such points, and its purpose is to provide a memory access control device that automatically outputs an appropriate ready signal according to the wait time of the memory to be implemented. .

Means for Solving the Problems> A memory access control device of the present invention comprises a socket in which a plurality of memories with different weights are selectively mounted, and an address input from a CPU for each memory mounted in the socket. an address decoder that decodes and outputs a bus cycle extension time selection signal corresponding to the address area individually assigned to each address area, and an extension signal corresponding to each memory mounted in the socket that is output from this address decoder. a logic gate that provides an OR output of a time selection signal to a chip input terminal of the socket; and a wait time signal generator that outputs a plurality of wait time signals delayed in clock units according to the weight of each memory mounted in the socket. block, and generates a predetermined ready signal corresponding to the weight of each memory mounted in the socket based on the expansion time selection signal output from the address decoder and the wait time signal output from the wait time signal generation block. It is characterized in that it includes a logic gate block that outputs the data to the CPU.

Functions> In the present invention, the address decoder decodes the input address into a bus cycle expansion time selection signal corresponding to the address area individually assigned to each memory, and outputs the signal.

Among the expansion time selection signals output from this address decoder, the OR output of the expansion time selection signals corresponding to multiple memories with different wait times mounted on a common socket is sent to the chip enable terminal of the socket via a logic gate. given to.

On the other hand, the wait time signal generation block outputs a plurality of wait time signals delayed in clock units according to the weight of each memory.

The logic gate block automatically generates a predetermined ready signal corresponding to the weight of each memory based on the expansion time selection signal output from the address decoder and the wait time signal output from the wait time signal generation block. and output to the CPU.

As a result, a predetermined wait time is automatically set for each memory according to its access time, and data can be stably read and written even for memories whose access time is slower than the CPU's access time. Ru.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as in FIG. 3 are given the same reference numerals. In the figure, 16 is an address decoder, and each memory 4, which is mounted with an address ADH input from a CPU (not shown),
8. Bus cycle expansion time selection signal W according to the address area individually assigned for each 8.11
O,WIW2. Decode to W3 and output. The expansion time selection signal WO is output to the OR gate 2 and is applied to the chip 1 select 1~ terminal of the first memory 4 via the inverter 3, and the expansion time selection signal W1 is output to the AND gate 5.
The expansion time selection signal W2 is output as a gate control signal to the AND gate 6 and applied to the chip select terminal of the second memory 8 via the NOR gate 17. The expansion time selection signal W3 is applied to the chip select terminal of the second memory 8, and is output as a wait time signal to the AND gate 9, and is also applied to the chip select terminal of the third memory 11 via the inverter 10. . Note that the memory 8 of this embodiment also has two types (wait 1 and wait 2) with different wait times as shown in FIG.
shall be selectively removably installed via a common socket.

In such a configuration, the address ADH assigned to each memory 4, 8, or 11 to be mounted is applied to the address decoder 16 from the CPU. In other words, when a 1-wait memory is implemented as memory 8, 1
Pf in the weight memory! : The address ADR of the unique area allocated is input, and if a 2-way memory is implemented as memory 8, the address ADR of the unique area allocated to the 2-way memory is input.
is input.

When a 1-wait memory is implemented as memory 8,
An expansion time selection signal W1 from the address decoder 16 is applied to the AND gate 5 and also applied to the chip select terminal of the memory 8 via the NOR gate 17. Also,
AND gate 5 outputs wait time signal WTI applied from D-type flip-flop 12 to CPU via OR gate 2 as ready signal RDY. This results in
The CPU extends the bus cycle by one clock and executes reading and writing of data to and from the one-wait memory 8.

When a 2-way memory is implemented as memory 8,
Extension time selection signal VAT 2 from address decoder 16
is added to AND gate 6 and Noah gate 17
The signal is applied to the chip select terminal of the memory 8 via.

Furthermore, the AND gate 6 outputs the wait time signal WT2 applied from the D-type flip-flop 13 to the CPU via the OR gate 2 as a ready signal RDY. As a result, the CPU extends the bus cycle by two clocks and
Data is read and written to and from the wait memory 8.

When selecting these wait times, there is no need for manual switch switching as in the prior art, and the process is automatically executed just by setting on the program.

Incidentally, the timing diagram of such a series of operations is substantially the same as that shown in FIG. 3 described above.

In addition, in the above embodiment, an example was described in which a memory with a weight of O is used as the memory 4, two types of memories of 1 weight and 2 weight are selectively used as the memory 8, and a memory with a weight of 3 is used as the memory 1]. , various combinations are possible without being limited to these combinations.

Furthermore, the logic gates used in the present invention are not limited to the combinations of the embodiments, but can be modified in various ways depending on the circuit configuration.

Further, the present invention can be applied to, for example, a system A/E of MS-DO3.
M S (EXPANDED MEMORY 5PEC
When memory expansion is performed using IFICAT1ON), it is possible to achieve this more easily by simply changing the mapping of the EMS, and there is no need to change the mapping of the main body program.

<Effects of the Invention> As described above, according to the present invention, a memory access control device that automatically outputs an appropriate ready signal according to the wait time of the mounted memory can be realized with a relatively simple configuration. This is effective for control when there is a difference in access time between the CPU and memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a conventional device, and FIG. 3 is a timing chart explaining the operation of FIG. 2...OR gate, 3.10...Inverter, 4゜8.11...Memory, 5.6.9...And gate,
12-14...D-type flip-flop, Russ decoder, 17...Noah gate.

Claims (1)

[Scope of Claims] A socket in which a plurality of memories with different weights are selectively mounted, and an address input from a CPU to an address area individually allocated to each memory mounted in this socket. an address decoder that decodes and outputs an expansion time selection signal of the corresponding bus cycle, and a logical OR output of the expansion time selection signal corresponding to each memory mounted in the socket, which is output from this address decoder, to the chip of the socket. a logic gate applied to an enable terminal; a wait time signal generation block that outputs a plurality of wait time signals delayed in clock units according to the weight of each memory mounted in the socket; and an expansion output from the address decoder. A logic gate block that generates a predetermined ready signal corresponding to the weight of each memory mounted in the socket based on the time selection signal and the wait time signal output from the wait time signal generation block and outputs it to the CPU. A memory access control device characterized by: