JPH0322491A - Manufacture of thin-film integrated circuit - Google Patents

Manufacture of thin-film integrated circuit

Info

Publication number
JPH0322491A
JPH0322491A JP15760089A JP15760089A JPH0322491A JP H0322491 A JPH0322491 A JP H0322491A JP 15760089 A JP15760089 A JP 15760089A JP 15760089 A JP15760089 A JP 15760089A JP H0322491 A JPH0322491 A JP H0322491A
Authority
JP
Japan
Prior art keywords
film
thin
conductor layer
thin film
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15760089A
Other languages
Japanese (ja)
Inventor
Mikio Baba
馬場 幹夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15760089A priority Critical patent/JPH0322491A/en
Publication of JPH0322491A publication Critical patent/JPH0322491A/en
Pending legal-status Critical Current

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To prevent a flaw, a stain, a smear, oxidation and others of a conductor layer and thereby to improve reliability by a method wherein a thin-film resistance layer and the conductor layer are stacked on an insulative substrate, an insulative thin film is so formed on the conductor layer as to be used as a protection film for the conductor layer in processes of patterning and heat treatment, and this insulative thin film is removed after the heat treatment. CONSTITUTION:A thin-film resistance layer 2 is formed on an insulative substrate 1. A thin-film conductor layer 3 is deposited thereon and an silicon oxide film 4 is deposited further this layer. A photoresist film 5 is applied thereon by coating and exposure-development and patterning are applied. With this film used as a mask, subsequently, the silicon oxide film 4 and the thin film conductor layer 3 are etched to be removed sequentially and the thin-film conductor layer 3 is patterned. After the photoresist film 5 is removed, a photoresist film 6 is applied on the whole surface by coating and patterned, and with this film used as a mask, the thin-film resistance layer 2 is etched, so as to form a resistance layer pattern. After the photoresist film 6 is removed, subsequently, heat treatment is executed to remove the silicon oxide film 5, and thus a thin- film integrated circuit is constructed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は薄膜集積回路の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing thin film integrated circuits.

〔従来の技術〕[Conventional technology]

従来の薄膜集積回路の製造力法は、第2図(a)に示す
ように、絶縁基板1の上に−90xlO−’/tの抵抗
温度係数を有する窒化タンタル薄膜からなる薄膜抵抗層
2をマグネトロンスパッタ法により形威し、薄膜抵抗層
2の上にNiCr/Au,Ti/Pa/Au,Aj 等
の薄膜導体層3を堆積し、薄膜導体層3の上にホトレジ
スト膜5を塗布してパター二ンをマスクとして薄膜導体
層3をエッチングして導体層パターンを形或する。
As shown in FIG. 2(a), the conventional method for manufacturing thin film integrated circuits involves forming a thin film resistance layer 2 made of a tantalum nitride thin film having a resistance temperature coefficient of -90xlO-'/t on an insulating substrate 1. A thin film conductor layer 3 of NiCr/Au, Ti/Pa/Au, Aj, etc. is deposited on the thin film resistance layer 2 by magnetron sputtering, and a photoresist film 5 is applied on the thin film conductor layer 3. Using the pattern 2 as a mask, the thin film conductor layer 3 is etched to form a conductor layer pattern.

次に、第2図(c)に示すように、ホトレジスト膜5を
除去した後、ホトレジスト膜6を塗布してパターニング
し、ホトレジスト膜6をマスクとして薄膜抵抗層2をエ
ッチングし導体積層して設ける。
Next, as shown in FIG. 2(c), after removing the photoresist film 5, a photoresist film 6 is applied and patterned, and the thin film resistance layer 2 is etched using the photoresist film 6 as a mask to form a conductive layer. .

次に、第2図(d)に示すように、ホトレジスト膜6を
除去した後、薄膜抵抗層2の経時的安定性を得るため空
気中で250〜450℃の熱処理を行い薄膜集積回路を
構或する。
Next, as shown in FIG. 2(d), after removing the photoresist film 6, heat treatment is performed in air at 250 to 450°C to obtain stability over time of the thin film resistive layer 2, and a thin film integrated circuit is constructed. There is.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の薄膜集積回路の製造方法は、薄膜導体層
の上に塗布したホトレジスト膜が゛薄膜導体層をバター
二冫グした後のホトレジスト膜の剥離工程で生ずる残渣
のために導体層上に汚れやじみを作b1パターン形成時
は、傷を生じて信頼性を低下させるという問題点があっ
た。
In the conventional thin film integrated circuit manufacturing method described above, the photoresist film coated on the thin film conductor layer is not coated on the conductor layer due to the residue generated in the process of peeling off the photoresist film after butter-buttering the thin film conductor layer. When forming the b1 pattern, there was a problem in that it caused scratches and reduced reliability.

筐た、M系の薄膜導体層を使用した場合、パターン形成
後、薄膜抵抗層の経時的安定性を得るための熱処理を行
うと、M膜表面が酸化しやすく、接触抵抗発生の原因と
なb1薄膜抵抗層の測定精度に悪影響を及ぼすという欠
点がある。
When an M-based thin film conductor layer is used in the case, if heat treatment is performed after pattern formation to obtain stability over time of the thin film resistance layer, the surface of the M film is likely to oxidize, which may cause contact resistance. There is a drawback that the measurement accuracy of the b1 thin film resistance layer is adversely affected.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の薄膜集積回路の製造方法は、絶縁基板上に薄膜
抵抗層及び薄膜導体層を順次積層して設ける工程と、前
記薄膜導体層の上に耐酸化性絶縁膜を形成する工程と、
前記絶縁膜及び前記薄膜導体層を選択的に順次エッチン
グして導体積層して設ける工程と、前記薄膜抵抗層を選
択的にエッチングして抵抗層パターンを形或する工程と
、前記抵抗層の安定化のための熱処理を行った後前記絶
縁膜を除去する工程とを含んで構成される。
The method for manufacturing a thin film integrated circuit of the present invention includes the steps of: sequentially laminating and providing a thin film resistance layer and a thin film conductor layer on an insulating substrate; forming an oxidation-resistant insulating film on the thin film conductor layer;
A step of selectively etching the insulating film and the thin film conductor layer to form a conductor layer; a step of selectively etching the thin film resistive layer to form a resistive layer pattern; and stabilizing the resistive layer. The method includes a step of removing the insulating film after performing a heat treatment for oxidation.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(e)は本発明の一実施例を説明するた
めの工程順に示した断面図である。
FIGS. 1(a) to 1(e) are cross-sectional views shown in the order of steps for explaining one embodiment of the present invention.

まず、第1図(a)に示すように、ガラスやセラミック
等からなる絶縁基板1の上に薄膜抵抗層2として−90
X10″″7℃の抵抗温度係数を有する窒化タンタル薄
i監成し、薄膜抵抗層2の上に薄膜導体層3としてTi
/Pd/Au又はM薄膜をマグネトロンスパッタ法によ
う0.4μmの厚さに堆積し、薄膜導体層3の上に高周
波スパッタ法によう約1μmの厚さの酸化シリコン膜4
を堆積する。次に、酸化シリコン膜4の上にホトレジス
ト膜5を塗布して露光・現像を行いパターニングする。
First, as shown in FIG. 1(a), a thin film resistance layer 2 is formed on an insulating substrate 1 made of glass, ceramic, etc.
A thin film conductor layer 3 of tantalum nitride is formed on the thin film resistance layer 2 with a temperature coefficient of resistance of
/Pd/Au or M thin film is deposited to a thickness of 0.4 μm by magnetron sputtering, and a silicon oxide film 4 of about 1 μm thick is deposited on the thin film conductor layer 3 by high frequency sputtering.
Deposit. Next, a photoresist film 5 is coated on the silicon oxide film 4 and patterned by exposure and development.

次に、第1図(b)に示すように、ホトレジスト膜5を
マスクとして酸化シリコン膜4及び薄膜導体層3を順次
エッチングして除去し、薄膜導体層3をパターニングす
る。
Next, as shown in FIG. 1(b), the silicon oxide film 4 and the thin film conductor layer 3 are sequentially etched and removed using the photoresist film 5 as a mask, and the thin film conductor layer 3 is patterned.

次に、第1図(C)に示すように、ホトレジスト膜5を
除去した後全面にホトレジスト膜6を塗布してパターニ
ングし、ホトレジスト膜6をマスクとして薄膜抵抗層2
をエッチングし抵抗積層して設ける。
Next, as shown in FIG. 1(C), after removing the photoresist film 5, a photoresist film 6 is applied and patterned on the entire surface, and the thin film resistive layer 2 is formed using the photoresist film 6 as a mask.
It is provided by etching and laminating the resistor.

次に、第1図(d)に示すようにJホトレジスト膜6を
除去した後薄膜抵抗層の経時的安定性を得るため、空気
中で250℃〜450℃の熱処理を行う。
Next, as shown in FIG. 1(d), after removing the J photoresist film 6, heat treatment is performed in air at 250 DEG C. to 450 DEG C. in order to obtain stability over time of the thin film resistance layer.

次に、第1図(e)に示すように、酸化シリコン膜4を
除去して薄膜集積回路を構成する。
Next, as shown in FIG. 1(e), the silicon oxide film 4 is removed to form a thin film integrated circuit.

このことによって、レジストの剥離不十分による導体膜
上の汚れやじみの発生を防ぎ、M膜を薄膜導体層に使用
した場合にはM膜の表面酸化を防止することができる。
This prevents stains and smearing on the conductor film due to insufficient peeling of the resist, and prevents surface oxidation of the M film when the M film is used as a thin film conductor layer.

なお、酸化シリコン膜の代bに窒化シリコン膜を使用し
ても良い。
Note that a silicon nitride film may be used in place of the silicon oxide film b.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、絶縁性基板上に薄膜抵抗
層及び導体層を順次積層して設け、導体眉の上に絶縁性
薄膜を形威してパターニング及び−5− 熱処理工程にかける導体層の保護膜とし、熱処理後、こ
の絶縁性薄膜を除去することによって、パターン形成時
にかける導体層の傷やホトレジスト膜の残留等による導
体層表面の汚れ、しみたとを防ぐことができ、1た、熱
処理による導体層表面の酸化を防止して信頼性を向上さ
せるという効果を有する。
As explained above, in the present invention, a thin film resistance layer and a conductor layer are sequentially laminated on an insulating substrate, and the insulating thin film is formed on the conductor layer, and the conductor is subjected to a patterning and heat treatment process. By removing this insulating thin film after heat treatment, it is possible to prevent stains and stains on the surface of the conductor layer due to scratches on the conductor layer during pattern formation and residual photoresist film, etc. It also has the effect of preventing oxidation of the conductor layer surface due to heat treatment and improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(e)は本発明の一実施例を説明するた
めの工程順に示した断面図、第2図(a)〜(d)は、
従来の薄膜集積回路の製造方法を説明するための工程順
に示した断面図である。 1・・・・・・絶縁基板、2・・・・・・薄膜抵抗層、
3・・・・・・薄膜導体層、4・・・・・・酸化シリコ
ン膜、5,6・・・・・・ホトレジスト膜。
FIGS. 1(a) to (e) are cross-sectional views shown in the order of steps for explaining one embodiment of the present invention, and FIGS. 2(a) to (d) are
1A and 1B are cross-sectional views illustrating a conventional method for manufacturing a thin film integrated circuit in order of steps. 1...Insulating substrate, 2...Thin film resistance layer,
3... Thin film conductor layer, 4... Silicon oxide film, 5, 6... Photoresist film.

Claims (1)

【特許請求の範囲】[Claims]  絶縁基板上に薄膜抵抗層及び薄膜導体層を順次積層し
て設ける工程と、前記薄膜導体層の上に耐酸化性絶縁膜
を形成する工程と、前記絶縁膜及び前記薄膜導体層を選
択的に順次エッチングして導体層パターンを形成する工
程と、前記薄膜抗抗層を選択的にエッチングして抵抗層
パターンを形成する工程と、前記抵抗層の安定化のため
の熱処理を行った後前記絶縁膜を除去する工程とを含む
ことを特徴とする薄膜集積回路の製造方法。
A step of sequentially laminating and providing a thin film resistance layer and a thin film conductor layer on an insulating substrate, a step of forming an oxidation-resistant insulating film on the thin film conductor layer, and a step of selectively stacking the insulating film and the thin film conductor layer. a step of sequentially etching to form a conductive layer pattern; a step of selectively etching the thin film anti-resistance layer to form a resistive layer pattern; A method for manufacturing a thin film integrated circuit, comprising the step of removing a film.
JP15760089A 1989-06-19 1989-06-19 Manufacture of thin-film integrated circuit Pending JPH0322491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15760089A JPH0322491A (en) 1989-06-19 1989-06-19 Manufacture of thin-film integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15760089A JPH0322491A (en) 1989-06-19 1989-06-19 Manufacture of thin-film integrated circuit

Publications (1)

Publication Number Publication Date
JPH0322491A true JPH0322491A (en) 1991-01-30

Family

ID=15653262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15760089A Pending JPH0322491A (en) 1989-06-19 1989-06-19 Manufacture of thin-film integrated circuit

Country Status (1)

Country Link
JP (1) JPH0322491A (en)

Similar Documents

Publication Publication Date Title
JPS61171131A (en) Formation of patterned conductive layer on semiconductor
JP4711249B2 (en) Superconducting integrated circuit and manufacturing method thereof
US3220938A (en) Oxide underlay for printed circuit components
JP3935687B2 (en) Thin film resistance element and manufacturing method thereof
JP4984855B2 (en) Thin film chip resistor, thin film chip capacitor, and thin film chip inductor manufacturing method
JPH10308397A (en) Electrode terminal and method of manufacturing the same
JPH07202425A (en) Method for manufacturing multilayer wiring board
JPH03104127A (en) How to form fine patterns
JP2756749B2 (en) Manufacturing method of moisture sensitive element
JPH07245303A (en) Method for manufacturing metal thin film resistor
JPH07273280A (en) Method of forming thin film pattern
JPS5816545A (en) Manufacture of semiconductor device
JP2580681B2 (en) Method for manufacturing semiconductor device
JP2533088B2 (en) Method of manufacturing thermal head
JPH0620230A (en) Thin-film magnetic head and its manufacture
JP2699924B2 (en) Ceramic substrate and method of manufacturing the same
JPH0114718B2 (en)
KR0147995B1 (en) A method for patterning a thin film head
JP2005277329A (en) Wiring board manufacturing method
JPH0234966A (en) Patterning of metal electrode on amorphous semiconductor thin film
JPH01298740A (en) Semiconductor device
JPH04127559A (en) Hybrid integrated circuit
KR0171142B1 (en) Contact hole wiring method of optical path control device
JPH0563366A (en) Manufacture of ceramic multilayer wiring board
JPH054362A (en) Method of manufacturing thermal head