JPH0323652A - Semiconductor pattern structure - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern design structure in IC design.

[Conventional technology]

FIG. 3 is a plan view showing an example of a conventional semiconductor pattern structure. In the diagram, (1) is the power supply bond, (21 is the GND
Wiring, 《3》 is the silicon gate that constitutes the gate electrode of the transistor, (4) is the well separation part that separates the P-type and N-type transistors in the CMOS structure, and (Is) is the part for transmitting the output signal of the transistor. Output signal m,
(61 is a diffusion layer that constitutes the source and drain of the transistor, and αd is a signal line that transmits a signal to the gate of the transistor.

Next, the operation will be explained. A signal is supplied from the signal clamp αO to the gate silicon (3), which is the gate electrode of the transistor. At this time, the gates of the P-type and NW transistors are at a certain level, and either p9J or Npn transistor is It becomes “ON” state and the ff source wiring (1)
Alternatively, it is supplied from either one of the GND wiring (21) and supplies a constant normal pressure signal to the output signal line (5).

[Problem to be solved by the invention]

Since the conventional semiconductor pattern structure is configured as above, when the signal is transmitted to the gate silicon,
Due to the resistance of the material and the parasitic capacitance with the surroundings, the further away from the connection between the signal gauze and the gate silicon, the longer the signal arrives, causing problems in high-speed response.

This invention was made to eliminate the above-mentioned problems, and its purpose is to obtain faster response by reducing the time delay of the gate silicon and creating an even transmission state. do.

[Means of power to solve problems]

The semiconductor pattern structure according to the present invention aims to eliminate delays in signal transmission to transistors by connecting low resistance wires in parallel at two or more locations, thereby making the distribution of delays in signal transmission to transistors uniform. .

[Effect]

In the semiconductor pattern structure according to the present invention, by connecting low-resistance interconnections in parallel, the transmission delay to the transistors is uniformized in a faster direction, and thereby the transistor operation can be made faster.

Furthermore, the gate voltage of the transistor can be changed instantaneously due to the parasitic capacitance generated between the interconnections.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 is a plan view showing the semiconductor pattern structure, Figure 2 is m
FIG. 1 is a sectional view taken along line A-A shown in FIG.

In the figure, (1) to (6) and 0 (I) are the same as those shown in the conventional example of FIG. 3, so their explanation will be omitted.

《7》 is a low-resistance wiring that equalizes the transmission delay to the transistor gate, (8) is an oxide film for pure signal insulation, (9)
is a parasitic barrier that occurs between wiring lines.

Next, the operation will be explained. flK31-'mnAs explained in the conventional example, the signal from the signal IililaQ is transmitted to the gate silicon (3) from the connection part. 7) is also transmitted at the same time, and is transmitted to the gate of the transistor having a large resistance component at two or more locations through the low resistance wiring <<7>>.

As a result, the transistor's S O N # S
OFF' is faster. Either the PW or NW transistor is in the 'ON' state, and a signal is transmitted from the source wiring (1) or the GND ii'' line (2) to the output signal line (5).

〔Effect of the invention〕

As described above, the conductor pattern structure according to the present invention can speed up signal transmission to the gate of the transistor and increase the speed of operation.

[Brief explanation of drawings]

FIG. 1 shows a semiconductor pattern ma according to an embodiment of the present invention.
FIG. 3 is a plan view of a conventional semiconductor pattern structure. FIG. In the figure, (1) is the power source, (21 is the GN
D wiring, (3) is silicon gate, (4) is well front part, (5) is output signal line, (6) is diffusion counterfeit, (7) is low resistance wiring, (8) is oxide film, (9) represents parasitic capacitance, and aO represents signal quality. In addition. The same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] A semiconductor pattern structure characterized by having a function of connecting low-resistance wiring in parallel with the gate wiring of a transistor through two or more contacts to alleviate signal transmission delays and transmit signals at higher speed.