JPH0323716A - Output circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Separation] This invention relates to an output circuit, and in particular, when outputting low data, the gate potential of an n-type transistor connecting an output terminal and a ground electrode (GND) is rubbed in two stages. The present invention relates to an output circuit that enables this.

[Conventional technology]

FIG. 3 shows a circuit diagram of a conventional output circuit. In Figure E, 1 and 2 are n-type MOS transistors, L is an inductance, C is a capacitor, φ1, lI1! is the input signal shown in FIG. When the output is High, Il1
1=H,φ. = L, and when the output is Low, h '' L + φ, = H. Normally, the wiring connected to the output has an inductance component L and a capacitance C, so for example, when the output changes from High to Low, Ringing occurs as shown in Figure 4. The rise from the ground electrode (GND) at this time is called VOL.

In particular, in a CMOS type dynamic memory, the input signals φ1 and φ2 are generated by a CMUS inverter and have a waveform with very sharp rises and falls.

Furthermore, in order to increase the driving capability, the sizes of the output stage transistors 1 and 2 are also often increased.

[Problem to be solved by the invention]

Since the conventional output circuit was configured as described above,
Like dynamic memory, the VOL standard is 0.4
In the case of VOL, there is a problem that output ringing occurs due to the size of the inductance component L1 and C, exceeding the VOL standard of 0.4V.

This invention was made to solve the above-mentioned problems, and an object thereof is to obtain an output circuit that can prevent output ringing.

[Means for Solving the Problems] The output circuit according to the present invention has an output terminal and a ground electrode (GND).
) is the gate potential of one n-type transistor connected to 2
The voltage is raised to VCC in stages.

(Function) When the output circuit according to the present invention generates low data, the gate potential of the n-type transistor that is pulled to GND is set to 2.
By stepping up to VCC, output ringing is prevented.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an output circuit according to an embodiment of the present invention. In the figure, 1 to 5, 7 are n-type transistors, 8 is an inverter, 9 is a p-type transistor, 6 is a delay circuit, R1, R are resistances, L is an inductance component, C is a capacitance, and input signals ψ1, ψ2 is the timing shown in FIG.

Furthermore, % VRI! F is an arbitrarily set potential, and here it is generated by resistance division using resistors R1 and R2, but other transistors, diodes, etc. may also be used. VREF is set slightly higher than Vth of the n-type transistor 2.

The next six operations will be explained.

First, the input signal ψ1 is High and the input signal ψ is Low.
In the case of w, n-type transistor l is ON1 n-type transistor 2 is OFF L/, so the output data is High.
becomes. Next, the input signal ψ1 changes from High to Low,
When ψ changes from Low to High, transistor 5 is first turned on and the potential of node N increases to VREF.

In other words, when transistor 2 is in the non-saturation region, ONL/, the output attempts to become Low. However, since the driving ability of transistor 2 is small due to the non-saturation region, the period T in FIG.
As shown in Fig. 1, it attempts to gradually shift to the Low side.

After that, with a certain delay, N becomes High, and a signal of the opposite phase turns off the transistor 7.
N-type transistor 3# and P-type transistor 9 are turned on, the potential of node N becomes Vcc, and output data is pulled to ground electrode GND.

[Effects of the Invention] As described above, according to the present invention, in a dynamic memory cloud ζ with strict regulations for VOL of Low output (VoL
=0,4V) When outputting LOW data, it is possible to raise the gate potential of the n-type transistor that connects the output terminal and the ground electrode (GND) to the Vcc level in two steps, and the gate potential of the n-type transistor suddenly increases. The output ringing, that is, the rise in VOL that occurs when the voltage rises to Vcc can be suppressed by gently raising the gate potential to Vcc.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an output circuit which is an embodiment of the present invention.
2 shows a timing diagram of each signal in FIG. 1, FIG. 3 shows a circuit diagram of a conventional output circuit, and FIG. 4 shows a timing diagram of each signal in FIG. 3. In the figure, 1 to 5, 7 are n-type transistors, 6 is a delay circuit,
8 is an inverter, 9 is a P-type transistor, Rl e R
M is a resistance, L is an inductance component, and C is a capacitance. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] In a data output buffer composed of n-type transistors, one n
1. An output circuit characterized in that the gate potential of a type transistor is first set to a level as high as Vth of the n-type transistor when outputting low data, and then raised to Vcc.