JPH03244247A - Afc circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AFC circuit used to stabilize the center frequency of a digital modulation signal input to a demodulator when demodulating the digital modulation signal.

When demodulating a digitally modulated signal, an AFC circuit is generally used to suppress various frequency fluctuations in order to improve the demodulation characteristics of the demodulation circuit, especially the bit error rate characteristics. However, it is common practice to stabilize the center frequency of the digital modulation signal input to the demodulation circuit. A conventional example of such an AFC circuit is shown in FIG.

In the figure, the frequency conversion circuit 100 has an input BPF (
bandpass filter) 101. Mixer 102, voltage controlled oscillator (VCO) 103, IF BPF 104
, and an IF amplifier 105, among which the BPFI
The OI 104 and IF amplifier 105 are designed to have relatively wideband characteristics so as not to affect the phase and amplitude characteristics of the digital modulation signal.

Next, the demodulation circuit 106 is composed of a band-limiting BPF 107, a phase detector 108, and a carrier recovery circuit 109. The band-limiting BPF 107 limits the band of the digital modulation signal and improves the demodulation characteristics by improving the C/N. Contribute to improvement.

The demodulation of the digital modulation signal is performed by combining the digital modulation signal input from the frequency conversion circuit 100 and the carrier wave f input from the carrier wave regeneration circuit 109 into the phase detector 108 .

It can be demodulated by multiplying and combining, and the example in Fig. 6 is an example where the digital modulation signal is a four-phase orthogonal modulation signal,
Two orthogonal signals, I and Q, are demodulated as demodulated signals. The carrier wave reproducing circuit 109 synchronizes the carrier wave with the center frequency of the digital modulation signal using the demodulated two signals I and Q, and outputs a synchronization detection signal 110 which is a signal for determining whether the synchronization or asynchronization is present.

The AFC circuit 111 includes a frequency divider 112 that divides the frequency of the digital modulation signal that has passed through the band-limiting BPF 107 by A, a reference oscillator 113 that outputs a reference frequency signal, and a phase comparison between the frequency-divided digital modulation signal and the reference frequency signal. a phase comparator 116 that outputs an error signal, which is a child signal 114 when the phase of the digital modulation signal is ahead of the reference frequency signal, and a signal 115 when the phase is delayed;
A microprocessor 118 that controls vC0103 by changing the data of the D/A converter 117 according to the states of the synchronization detection signal output from the carrier wave regeneration circuit 109 and the error signal output from the phase comparator 116, thereby changing the AFC voltage. It consists of

Next, the operation of the AFC circuit will be explained. First, if the synchronization detection signal of the carrier regeneration circuit 109 is at a level indicating asynchronization, the microprocessor 118 frequency-sweeps the digital modulation signal input to the demodulation circuit 106 by frequency-sweeping the VCO 103. The output signal of 112 is changed and the phase is compared with the reference frequency signal by a phase comparator.

When the carrier wave fL is synchronized during sweep of the VCO 103, the synchronization detection signal 110 of the carrier wave regeneration circuit 109 becomes a level indicating synchronization, and the microprocessor 118
Stop the sweep of IO3, refer to the two error signals of the phase comparator 116, and if it is on the + side, control is performed to lower the oscillation frequency of the VCO 103, and conversely, if it is on the one side, the VCO I
Control is performed to increase the oscillation frequency of 03.

In this way, the microprocessor 118 converts the VCO via the D/A converter 117 so as to stabilize the frequency of the digital modulation signal input to the demodulation circuit 106.
103. In addition, in order to prevent the oscillation frequency of the VCO 103 from being changed frequently when the carrier wave fL is synchronized, a tolerance range is set for the phase comparator 116 to suppress the control frequency of the oscillation frequency of the VCO 103.
Suppress frequency fluctuations of the reproduced carrier wave.

By the way, in the above conventional example, the frequency-divided digital modulation signal input to the phase comparator 116 is passed through the band-limiting BPF.
107, it is affected by the characteristics of the band limiting BPF 107. In particular, the digital modulation signal undergoes phase modulation or amplitude modulation due to changes in phase and amplitude characteristics due to temperature changes, and the frequency-divided digital modulation signal has a difference in height from the frequency that should be originally divided, causing the phase comparator 1
Errors can occur in the 16 error signals. Further, when the C/N is low, a frequency division error occurs in the output of the frequency divider 116, which causes a frequency error. Since the phase comparator is used as a means for stabilizing the digital modulation signal, not only the reference oscillator 113 is required, but also the configuration of the phase comparator 116 becomes complicated by providing a tolerance range. Furthermore, in order to compress the spread of the spectrum of the digital modulation signal, the final
It is necessary to divide the frequency to a certain degree, so that the digital modulation signal is
If the frequency is 00M82 or more, the frequency must be divided by 10,000 or more, which has the disadvantage that the number of stages of the frequency divider 112 increases. Moreover, jitter occurs in the frequency-divided signal, which has a negative effect when phase comparison is performed by the phase comparator 116.

The present invention solves these problems and not only has a simple configuration and can reduce costs, but also stabilizes the frequency of the digital modulation signal input to the demodulation circuit without being affected by the temperature characteristics of the circuit elements. It is an object of the present invention to provide an AFC circuit that can also stabilize a reproduced carrier wave.

In order to achieve the above object, the present invention provides a frequency conversion circuit that includes a voltage controlled oscillator and that converts the frequency of an input digital modulation signal, a carrier wave for demodulation, and a frequency conversion circuit that converts the frequency of an input digital modulation signal, a carrier wave for demodulation, and a frequency conversion circuit that converts the frequency of an input digital modulation signal. a demodulation circuit that demodulates the digital modulation signal frequency-converted by the frequency conversion circuit, the demodulation circuit including a carrier regeneration circuit that outputs a synchronization detection signal indicating whether or not the synchronization signal is input to the demodulation circuit. In the AFC circuit for controlling the voltage controlled oscillator so as to frequency-stabilize the frequency-converted digital modulation signal, the AFC circuit includes a microprocessor and a carrier wave output from the carrier wave regeneration circuit divided by m (however, m m≧2); a counter that is controlled by the microprocessor and counts the carrier wave frequency-divided by m by the frequency divider for a certain period of time and provides the counted value to the microprocessor; and a D/A converter that is controlled by the microprocessor based on the numerical value and the synchronization detection signal and outputs an AFC voltage for controlling the oscillation frequency of the voltage controlled oscillator.

According to this configuration, the frequency of the carrier wave regenerated by the carrier wave regeneration circuit is directly divided, the frequency-divided carrier wave is counted by a counter for a certain period of time, and the microprocessor uses the counted value and the synchronization detection signal to The voltage controlled oscillator is controlled via the /A converter, and the digital modulation signal input to the demodulation circuit is stabilized.

EXAMPLE 4 - Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing an example of the AFC circuit of this embodiment. In this figure, parts having the same functions as those of the conventional example shown in FIG. 6 are designated by the same reference numerals.

The AFC circuit 1 of this embodiment includes a microprocessor 2, a frequency divider 3 that divides the carrier wave f output from the carrier wave regeneration circuit 109 by m (where m is m≧2), and a frequency divider 3 that is controlled by the microprocessor 2 and divides the carrier wave f output by the carrier wave regeneration circuit 109. It is controlled by the microprocessor 2 using an N-bit counter 4 that counts the rotated carrier wave fL for a certain period of time, and a synchronization detection signal 110 output from the count value of the counter 4 and the carrier wave regeneration circuit 109 to control the oscillation signal of the VCO 103. D/A that outputs the AFC voltage of
117 converters are configured.

Next, the operation of this AFC circuit will be explained with reference to FIG. First, the synchronization detection signal 110 is at a level (
In FIG. 2, the microprocessor 2 changes the AFC voltage so that the D/A converter 11 generates a sawtooth wave as shown in FIG.
Send data to 7. The VCO 103 performs a frequency sweep using the AFC voltage, and the digital modulation signal inputted to the frequency conversion circuit 100 is frequency converted while being swept in the same manner as the change in the VCO 103, and is input to the demodulation circuit 5. The swept digital modulation signal passes through the band limiting BPF 107, and is combined with the carrier wave f output from the carrier regeneration circuit 109 by the phase detector 108, thereby demodulating the two signals of Q and Q.
The two signals are fed back to the carrier wave regeneration circuit 109, and when the carrier wave fL is synchronized, the synchronization detection signal 110 becomes a level indicating synchronization (°H" level in FIG. 2 (b)), and the microprocessor 2 Stop frequency sweep.

Next, the microprocessor 2 operates the N-bit counter 4 for a certain period of time using the control signal LE6, and counts the carrier waves frequency-divided by m. After counting for a certain period of time, the counted value is input to the microprocessor 2 via the signal line 7. The microprocessor 2 compares the reference value set in the program of the microprocessor 2 with the counted value, and if an error occurs, sends data to the D/A converter 117 to cancel the error, causing the VCO 103 to oscillate. By changing the frequency, the frequency of the digital modulation signal input to the demodulation circuit 5 is finely adjusted and stabilized, thereby stabilizing the reproduced carrier wave. As mentioned above, in this embodiment, since the frequency of the reproduced carrier wave fL is directly divided, the band-limiting BPF 1
It is characterized in that it is not affected by the temperature characteristics of 0.07, and that jitter does not occur in the frequency-divided signal and can be accurately counted with a counter. Furthermore, the configuration of this embodiment is extremely simple and can reduce costs.

Note that the frequency at which the oscillation frequency of the VCO 103 is changed during synchronization of the carrier wave regeneration circuit 109 is suppressed, and the regenerated carrier wave f
In order to suppress the frequency fluctuation of L, only the error exceeding the allowable error range may be corrected when comparing the counted value of the frequency-divided carrier wave with the reference value. Also, carrier wave f
(Instead of counting continuously and repeatedly, if you count at intervals of 1 second, for example, the VC
The frequency with which the oscillation frequency of O103 is changed is suppressed, and the frequency of the digital modulation signal input to the demodulation circuit 5 is further stabilized. Even with such a tolerance range,
Since this can be handled by a program on the microprocessor 2, there is no effect on the circuit.

Here, the design method will be explained using actual numerical values. If the center frequency of the digital modulation signal input to the demodulation circuit 5 is 140MHz, the reproduced carrier wave fL is also 140MHz.
It becomes MH2. The synchronization range of this carrier wave fL is usually set narrowly to prevent deterioration of C/N, for example, +/-IMHz. Set the division ratio of frequency divider 3 to 1740
Assuming that the operating time of the counter 4 is 2 msec, the count of the counter is 7000 counts, and the resolution at which the carrier wave fL can be counted is 20 kHz.

7000 counts expressed in binary is ll0IIOIO
It becomes L100OB and becomes 13 bits. By the way, since the synchronization range of the carrier wave f is +/-IMHz, the counter has +/-50 counts (= +/-110010
Since it is sufficient to capture the range of B), an 8-bit counter is sufficient. Therefore, when selecting a counter, there is a degree of freedom in selecting an 8- to 13-bit counter in the above example. It is also possible to use a 12-bit counter and input the lower 8 bits to the microprocessor 2. Furthermore, a 7-bit counter may be used if the operating time of the counter is selected appropriately. As described above, if the frequency division ratio of the frequency divider and the operating time of the counter are appropriately selected in consideration of the synchronization range of the carrier wave fL, the AFC circuit can be configured extremely easily.

In FIG. 2, the repetitive waveform of the AFC voltage that sweeps the VCO 103 is a sawtooth wave, but the waveform is not limited to a sawtooth wave such as a triangular wave or a sine wave, and any waveform that can smoothly sweep the frequency of the VCO 103 may be used. Further, even if the level of the synchronization detection signal indicating synchronization or non-synchronization becomes the opposite level to the example shown in FIG. 2, there is no problem because it can be handled by the program.

FIG. 3 is a block diagram showing another embodiment in which the count value of the counter is input to the microprocessor. In the example above, the count value of the counter 4 requires a minimum of 7 bits of signal line 7, so if the microprocessor 8 does not have enough input terminals, the microprocessor 8 will output the count value when the count of the counter 4 is completed. , shift register 10 with control signal LE9.
The output of the counter 4 is input to the shift register 10 via the signal line 7, and the microprocessor 8 outputs the clock CK and inputs data 12 to the shift register 10. This allows the input terminals of the microprocessor 8 to be saved.

FIG. 4 is a block diagram showing another embodiment of the demodulation circuit. This demodulation circuit 13 converts the band-limiting BPFI 07 shown in FIG. 1 into a band-limiting LPF 14.1 for the demodulated baseband signal.
This is an example in which the number is replaced with 5. In this case, in the conventional example, the band of the digital modulation signal is not limited, so the spectrum spreads, and the jitter of the frequency-divided signal becomes large.
Further, if noise is added, there is a possibility that the AFC circuit will malfunction, but in this embodiment, since a reproduced carrier wave is used, there is no effect at all.

FIG. 5 is a block diagram showing another embodiment of the present invention. When the C/N of the digital modulation signal is good, even if the sweep speed of the sawtooth wave shown in FIG. 2 is fast, the carrier wave regeneration circuit 109
The carrier wave f is synchronized, but when the C/N becomes low, the carrier wave fL is not synchronized unless the sweep speed of the sawtooth wave is slowed down. For this reason, the sweep speed is usually slowed down assuming the case where the C/N of the digital modulation signal decreases.

Therefore, a C/N detection circuit 17 is provided in the AFC circuit 16,
The digital modulation signal from the frequency conversion circuit 100 is manually input to the C/N detection circuit 17, and the
/N is detected and the result is input to the microprocessor 18 as a several-bit digital signal. The microprocessor 18 determines the C/H level from the output of the C/N detection circuit 17, sets the corresponding sawtooth wave sweep speed, and controls the VCO 103. Compared to the case where the sweep speed of the sawtooth wave is fixed, when the C/N is good, the carrier waves are synchronized quickly. The position where the C/N detection circuit 17 is connected is not limited to the input of the frequency conversion circuit 100, but may be the output side or the output of the band limiting BPF 107 of the demodulation circuit 5.

In the above explanation, it is assumed that the digital modulation signal is a four-phase orthogonal modulation value code as in the conventional example, but it goes without saying that the AFC circuit of the present invention can be used for any digital modulation signal as long as it is a demodulation circuit that regenerates a carrier wave. Nor.

As explained above, according to the present invention, the voltage controlled oscillator is finely tuned when the carrier wave is synchronized, so it is not affected by the temperature characteristics of the circuit elements used, and the frequency-divided signal does not have jitter, so it is stable. It has the advantage of being very easy to operate, and has the advantage of being extremely simple in structure and reducing costs.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing an example of AFC voltage for explaining it, and FIG. 3 is a diagram showing an example of AFC voltage.
The figure shows another example of the configuration of the part that inputs the count value of the counter into the microprocessor, FIG. 4 shows another example of the configuration of the demodulation open part, and FIG. FIG. 2 is a configuration diagram showing an example. FIG. 6 is a configuration diagram showing a conventional example. 1.16... AFC circuit, 2.8.18... Microprocessor, 3... Frequency divider, 4... Counter, 5.13... Demodulation circuit, 10... Shift register, 14.15...
L PF, 17... C/N detection circuit, 1
00... Frequency conversion circuit, 103... Voltage controlled oscillator, 107... BPF, 108... Phase detector, 109... Carrier wave regeneration circuit.

Claims (1)

[Claims] (1) A frequency conversion circuit that includes a voltage controlled oscillator and converts the frequency of an input digital modulation signal, and outputs a carrier wave for demodulation and a synchronization detection signal that indicates whether or not the carrier wave is synchronized with the digital modulation signal. a demodulation circuit that demodulates the digital modulation signal frequency-converted by the frequency conversion circuit; An AFC circuit for controlling the voltage controlled oscillator so as to stabilize it, comprising: a microprocessor; a frequency divider that divides the carrier wave output from the carrier wave regeneration circuit by m (where m is m≧2); a counter that is controlled by a microprocessor and counts carrier waves frequency-divided by m by the frequency divider for a certain period of time and provides the counted value to the microprocessor; and a D/A converter that outputs an AFC voltage for controlling the oscillation frequency of the voltage controlled oscillator.