JPH03248434A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable high efficiency of an insulating gate type field effect transistor by forming a silicon-based amorphous thin film containing hydrogen, by forming a cap layer consisting of a substance whose diffusion coefficient of hydrogen is smaller than that of amorphous silicon dioxide and by desorpting and diffusing hydrogen existing in the amorphous thin film by a specified heat treatment. CONSTITUTION:A non-single crystalline silicon thin film 1-2, a gate oxide film 1-4, a gate electrode 1-5, a source region 1-6 and a drain region 1-7, and a layer insulating film 1-8 are formed one by one on an insulating amorphous material 1-1. An amorphous silicon film 1-9 containing hydrogen is deposited using a plasma CVD device at a substrate temperature of 200 deg.C or below, a cap layer 1-10 whose diffusion coefficient of hydrogen is smaller than of amorphous silicon dioxide is formed thereon, and hydrogen treating annealing is carried out at a temperature of 300 to 500 deg.C to desorpt and diffuse hydrogen. After hydrogen starts to desorpt, temperature increase speed is made slower than 5 deg.C/minute to restrain development of defects and peeling of the film. After the cap layer 1-10 and the amolphous silicon layer 1-9 are etched and removed, a contact electrode 1-11 is formed to complete a thin film transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device made using a non-single crystal semiconductor thin film.

[Prior Art] A large number of dangling bonds exist in non-single crystal semiconductor thin films such as amorphous silicon thin films, microcrystalline silicon thin films, and polycrystalline silicon thin films. For example, in polycrystalline silicon thin films, defects such as dangling bonds that exist at grain boundaries become trap levels for carriers and act as barriers to carrier conduction.
W, 5eto, J.

Appl, Phys., 46. p5247 (1975
)). Therefore, in order to improve the performance of polycrystalline silicon thin film transistors, it is necessary to reduce the defects. (J, A p p 1. P h Y s.

53 (2), p1193 (1982)),
For this purpose, the defects are terminated with hydrogen, and such hydrogenation methods include hydrogen plasma treatment, hydrogen ion implantation, and hydrogen diffusion from a plasma nitride film. Are known.

[Problems to be Solved by the Invention] However, conventional hydrogenation methods have the following drawbacks. (1) The hydrogen ion implantation method requires an expensive device called an ion implanter, and has drawbacks such as the difficulty of implanting hydrogen into a polycrystalline silicon layer with good control over several hundred people.

(2) In the hydrogen diffusion method from plasma nitride film,
Since the supply of hydrogen is insufficient, there are drawbacks such as the characteristics not being sufficiently improved compared to hydrogen plasma treatment. (3)
Although the hydrogen plasma treatment method is excellent in improving characteristics, it has drawbacks such as frequent occurrence of defects such as poor gate breakdown voltage and shift of threshold voltage (Vth) due to plasma damage.

Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned problems while ensuring the effect of improving TPT characteristics by hydrogenation.

[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention has the following features.

(1) In a method of manufacturing a semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, a step of forming an amorphous thin film mainly composed of silicon and containing hydrogen; The step of forming a cap layer made of a substance having a hydrogen diffusion coefficient smaller than that of amorphous silicon dioxide on the thin film, and the step of desorbing and diffusing hydrogen present in the amorphous thin film by heat treatment, In the heat treatment process, the heating rate from the temperature at which hydrogen starts dehydrogenating from the amorphous silicon to the predetermined annealing temperature is set to be t's lower than 5° C./min.

(2) The heat treatment temperature in the heat treatment step is 300°C to 500°C.
It is characterized by a temperature of about ℃.

(3) The amorphous thin film mainly composed of silicon and containing hydrogen is formed by a plasma CVD method.

(4) The substrate temperature when forming the amorphous thin film mainly composed of silicon and containing hydrogen by plasma CVD is 200°C.
It is characterized by being less than a certain degree.

(5) In a method of manufacturing a semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, a step of forming an amorphous thin film mainly composed of silicon and containing hydrogen; The step of forming a cap layer made of a substance having a hydrogen diffusion coefficient smaller than that of amorphous silicon dioxide on the thin film, and the step of desorbing and diffusing hydrogen present in the amorphous thin film by heat treatment, In the heat treatment process, the temperature is once 400℃~5
It is characterized by having at least a step of raising the temperature to a temperature of about 0.00 C or higher and annealing, and a step of cooling to about 400° C. or lower and annealing for a predetermined time.

[Embodiment] An embodiment of the present invention will be described in accordance with a process diagram of a thin film transistor according to the present invention shown in FIG.

FIG. 1(a) shows an insulating amorphous material 1-1 such as an insulating amorphous substrate such as glass or quartz, or an insulating amorphous material layer such as 5i02, and a non-conductive material such as polycrystalline silicon. In this step, a single crystal silicon thin film 1-2 is deposited, and after step 7, the non-single crystal silicon thin film is patterned by photolithography. As a method for forming the non-single crystal silicon thin film, there are the following methods.

(1) Deposit a polycrystalline silicon thin film at about 580° C. to 650° C. by low pressure CVD method.

(2) EB (Electron Beam) vapor deposition method,
After depositing an amorphous silicon thin film by sputtering, plasma CVD, etc., open-phase growth annealing is performed at about 550°C to 650°C for about 2 to 70 hours to form a polycrystalline film with large grains of 1 to 2 μm or more. Form a silicon thin film.

(3) After depositing a polycrystalline silicon thin film by low pressure CVD method etc.
After implanting Si or the like using the ion implantation method to make the polycrystalline silicon thin film amorphous, solid-phase growth annealing is performed at approximately 550°C to 650°C to form large-grained polycrystalline silicon with a grain size of approximately 1 to 2 μm. Forms a thin film.

In addition, when polycrystalline silicon is formed by the above method, there are cases where the crystallinity is close to 100%, literally polycrystalline silicon, and cases where the crystallinity is about 50% to 90%. There are cases.

In this case, it may be more appropriate to call the latter microcrystalline silicon rather than polycrystalline silicon, but in this patent, unless otherwise specified, both will be referred to as polycrystalline silicon. . Further, as the non-monocrystalline silicon thin film 1-2, microcrystalline silicon or amorphous silicon thin film may be used in addition to the above-mentioned polycrystalline silicon thin film.

Next, as shown in FIG. 1(b), a gate oxide film 1-4 is formed by a thermal oxidation method or the like. If dry oxidation is used, a high-quality gate oxide film with high dielectric strength can be obtained by heat treatment at about 1150° C. in an oxygen atmosphere. If a wet oxidation method is used, an oxide film can be formed even at a low temperature of about 900° C., but the dielectric strength is lower and the film quality is inferior compared to a film formed by a dry oxidation method. Said non-single crystal silicon thin film 1-
When polycrystalline silicon is used as 2, crystal growth due to heat treatment progresses in this thermal oxidation step, and the degree of crystallinity improves.
Grain size expands. Said non-single crystal silicon thin film 1-2
Even when an amorphous silicon thin film or a microcrystalline silicon thin film is used as
Crystals grow from 0A to polycrystalline silicon with a size of several μm. Note that the method for forming the gate oxide film is not limited to the above-mentioned thermal oxidation method, but also includes (1) CVD method, plasma CVD method,
Si by ECR-PCVD method, photoCVD method, sputtering method, etc.
Form an O2 film. (2) There is also a method of low temperature oxidation such as plasma oxidation. These methods allow the process temperature to be as low as about 600° C. or lower, so that an inexpensive glass substrate can be used as the substrate.

Next, as shown in FIG. 1(C), a gate electrode 1-5 is formed. Polycrystalline silicon is used as the gate electrode material. The method for forming the polycrystalline silicon layer is as follows: (1) Polycrystalline silicon is formed by low pressure CVD, and N″po
ly-Si formation method, (2) Form an amorphous silicon layer doped with impurities such as B (boron) and P (phosphorous) by plasma CVD method, etc., and heat it in the solid phase at about 550°C to 650°C. Growth annealing is performed for about 2 hours to about 70 hours,
By polycrystallizing the amorphous silicon layer, P-pol
There are methods such as forming y-5i, N"poly-3i. In particular, when forming the gate electrode using solid phase growth method, large grains containing crystal grains with a crystal grain size of 1 to 2 μm or more are available. Since it is possible to form polycrystalline silicon with a diameter of
"When poly-8i is used, there is an advantage that channel ion implantation can be omitted, but the details will be described later. Next, using the gate electrode 1-5 as a mask, impurity elements are ion-implanted to form the source region. 1-6 and drain region 1-7 are formed.As the impurity element,
Phosphorus, arsenic, boron, etc. are used.

Next, as shown in FIG. 1(d), a glabellar insulating film 1-8 is deposited. Subsequently, heat treatment is performed at approximately 600° C. to 1000° C. for the purpose of activating impurities in the source region 1-6 and drain region 1-7 and densifying the interlayer insulating film 1-8.

Next, as shown in FIG. 1(e), an amorphous silicon film 1-9 is formed.
is deposited by a method such as a plasma CVD method. At this time, the amorphous silicon thin film contains about 10% hydrogen. As an apparatus, a normal plasma CVD apparatus can be used.

A substrate is set in a reaction chamber, and monosilane gas or a gas obtained by diluting monosilane gas with hydrogen gas, argon gas, or the like is introduced into the reaction chamber. Internal pressure is 0.3~
It is set to about 2 Torr. A high frequency power of 13°56MHz is applied to decompose the above gas, and hydrogenated amorphous silicon (a-3i:H) is deposited on the substrate in a thickness of 500 to 1 μm.
form a degree. The substrate temperature is from room temperature to about 350° C., but is particularly preferably 200° C. or lower since hydrogen is efficiently desorbed by low-temperature annealing.

Subsequently, as shown in FIG. 1(f), a cap layer 1-10 is formed on the amorphous silicon film 1-9 and heated at 300°C to
Hydrogenation annealing is performed at a temperature of about 500° C., and the annealing time is about 30 minutes to 5 hours. Through this annealing, atomic hydrogen is desorbed from the amorphous silicon, diffuses into the interlayer insulating film and the gate electrode, and terminates dangling bonds existing at the grain boundaries of the polycrystalline silicon. Note that the cap layer 1-10 is preferably made of a material in which hydrogen generated from amorphous silicon does not easily diffuse. For example, (1
) A method of forming a metal thin film of Cr, Mo, AI, etc. to a thickness of about 300 to 1 μm by sputtering, vapor deposition, etc.; (2) A method of forming amorphous silicon nitride (a-3iNx) to a thickness of about 1000 to 1 μm. Particularly desirable. Note that the material of the cap layer is not limited to the above-mentioned materials, but it is important that it be a material in which hydrogen is more difficult to diffuse (has a smaller diffusion coefficient) than amorphous silicon dioxide (SiO2).

Next, a method of raising the temperature to a predetermined hydrogenation annealing temperature will be described. Since a cap layer is formed on amorphous silicon to prevent hydrogen diffusion, unless the hydrogenation annealing method is optimized, the amorphous silicon layer may peel off or pinholes may occur due to rapid desorption of hydrogen. This causes problems such as defects. Therefore, the conditions for hydrogenation annealing, particularly the method of raising the temperature to a predetermined hydrogenation annealing temperature, are important. FIG. 2 is an example of a schematic diagram of a temperature raising method in an embodiment of the present invention.

In Fig. 2, (a) shows that a sample is inserted into an annealing furnace maintained at a predetermined temperature, and a predetermined annealing temperature (T1
), and annealing is performed at a predetermined hydrogenation annealing temperature (TI). A temperature increase rate slower than 5°C/min will reduce defects due to hydrogen desorption. This is desirable because generation and film peeling are suppressed. However, the temperature increase rate does not always have to be constant, and may of course be varied within the above-mentioned range.

As mentioned above, T1 is preferably about 300°C to 500°C, and in particular, about 350°C to 400°C allows for efficient desorption of hydrogen from amorphous silicon and diffusion of the desorbed hydrogen. Furthermore, it is particularly desirable because the efficiency of adding hydrogen to the dangling bonds of polycrystalline silicon is high, and 400
At an annealing temperature of approximately 500°C to 500°C, desorption of hydrogen from amorphous silicon and diffusion of desorbed hydrogen occur more efficiently than at the above-mentioned temperatures; The efficiency of hydrogen addition decreases (because hydrogen addition and desorption occur simultaneously).

Therefore, the temperature is raised to about 00°C to 500°C or higher, annealed for about 10 minutes to 1 hour to promote hydrogen desorption and diffusion, and then cooled to about 400°C or less. An annealing method in which annealing is performed for about 30 minutes to 2 hours to promote the addition of hydrogen to defects such as dangling bonds in crystalline silicon is extremely effective. Figure 2 (b
) is heated to a predetermined temperature (T2) at a predetermined heating rate,
Subsequently, a predetermined temperature (TI) which is the hydrogenation annealing temperature
This shows the case where the temperature is increased at a slow rate until .

The reason for changing the heating rate before and after T2 is 2 as mentioned above.
Approximately 50°C to 300°C (The substrate temperature during film formation by plasma CVD is low, and a film formed at room temperature may lose hydrogen from around 150°C.) At higher temperatures, hydrogen may be released from the film. Since desorption of hydrogen begins, the temperature increase rate is changed before and after that, and after hydrogen desorption begins, the temperature increase rate is made slower than 5℃/min to suppress the occurrence of defects and peeling of the film. It's for a reason.

Therefore, it is desirable that T2 be approximately 200°C to 350°C. The heating rate may be faster than 5°C/min,
It also shortens the heating time.

Further, as in the case of FIG. 2(a), the temperature increase rate does not always need to be constant. Further, the change in temperature increase rate before and after T2 does not need to be stepwise, and the temperature increase rate may be changed gradually. Further, there may be a plurality of temperatures (T2) at which the temperature increase rate is changed. Figure 2(c) shows the case where the temperature is raised to a predetermined temperature (T2), held at T2 for a predetermined time, and then raised to a predetermined temperature T1, which is the hydrogenation annealing temperature. at a low temperature for a predetermined period of time (e.g. 20
By holding the film for about 1 minute to 2 hours, hydrogen can be removed more slowly, and the occurrence of defects and peeling of the film can be suppressed. T2 is preferably about 250°C to 350°C.
(If the substrate temperature is low and the film is formed near room temperature, T
2 is preferably about 150°C to 200°C.) Note that it is not necessary to keep the predetermined temperature (T2) constant. For example, the temperature may be raised slowly at a rate slower than 5°C/min. There may be more than one temperature (T2) to maintain at the temperature of be able to. In addition, Fig. 2 (a) to (C
) can be used in combination to further suppress the occurrence of defects and peeling of the film. Moreover, FIGS. 2(a) to 2(c) are examples of the present embodiment, and the present invention is not limited thereto.

Subsequently, as shown in FIG. 1(g), the cap layer 1 is
-10 and the amorphous silicon layer 1-9 are removed by etching, the contact electrode 1 of the source region and the drain region is removed.
-11, the thin film transistor is completed. As the contact electrode material, a metal material such as AI, Cr, or Ni is used.

Polycrystalline silicon TFT (pol
y-8i TFT) c7) Field effect mobility is 50 cm2/V-s in N channel (LP CVD method 5
When polycrystalline silicon is formed at 90°C) ~160c
m2/V −s (when amorphous silicon formed by plasma CVD is grown in solid phase at 600°C for about 17 hours)
So, in the case of just annealing in a hydrogen gas atmosphere (
~10cm2/V-s), the characteristics were significantly improved.

Next, we will discuss the problem of threshold voltage control associated with hydrogenation. When polycrystalline silicon TPT is hydrogenated, the N-channel transistor shifts vth in the depletion direction, and the P-channel transistor shifts in the enhancement direction;
By doping with an impurity of about m3, vth can be controlled. For example, in FIG. 1, before forming the gate electrode, there is a method of implanting an impurity such as B (boron) at a dose of about 10 to 1 Q + 37 cm 2 by ion implantation or the like. In particular, if the dose is around the above value, the P-channel transistor,
vth can be controlled so that the off-state current of both N-channel transistors is minimized. Therefore, 0MO3
Pch, Nc also when forming a type TFT
It is also possible to do channel doping over the entire surface in the same process without selectively doping h. In addition, as mentioned above, as the gate electrode, N″p
By using P′″poly-3i formed by solid phase growth method etc. instead of using oly-si, vth can also be controlled without using channel ion implantation.

Next, the reason why defects caused by plasma damage, which frequently occur in conventional hydrogen plasma processing, do not occur at all in the hydrogenation of the present invention will be described.

The cause of damage caused by hydrogen plasma processing is not clear at present, but immersion in a plasma atmosphere causes charge-up, resulting in a state in which voltage is applied to the gate film. Furthermore, since the substrate temperature is relatively high at around 300°C, a type of BT (Bias-Temp.
The phenomenon is well explained by a model in which TFTO failure occurs due to stress and the hydrogen plasma time being as long as 1 to 2 hours.

On the other hand, in the hydrogenation method of the present invention, amorphous silicon is formed by plasma CVD, and hydrogenation is performed using hydrogen atoms released from the amorphous silicon by annealing. Therefore, unless T stress is applied as described above during the formation of an amorphous silicon film, no damage will occur.

In fact, when amorphous silicon is simply formed by the plasma CVD method, almost no T stress is applied as described above, and the TPT formed according to the present invention was able to completely eliminate defects due to damage. There are two possible reasons for this:

(1) In hydrogen plasma treatment and amorphous silicon film formation,
Since the power of the high frequency wave is different by one order of magnitude (hydrogen plasma treatment = 100 to 200 W for an electrode size of 20 cm, amorphous silicon film formation: 10 to 20 W), charge-up is less likely to occur than in hydrogen plasma treatment.

(2) In hydrogen plasma treatment, it is necessary to diffuse hydrogen atoms to the polycrystalline silicon layer by thermal diffusion while decomposing hydrogen gas and supplying atomic hydrogen. Therefore, if the substrate temperature is not kept at a high temperature of about 250°C to 3500°C,
The effect of hydrogenation is drastically reduced. On the other hand, in the present invention, the supply of atomic hydrogen and hydrogenation by thermal diffusion are not carried out during the formation of the amorphous silicon film, but in a separate annealing process. The substrate temperature can be lowered. Also, lower the substrate temperature (for example, 20
In the present invention, it is preferable to lower the film formation temperature of amorphous silicon because hydrogen is more easily desorbed at a lower temperature when the temperature is lower than 0°C. Therefore, in the present invention, BT stress is further reduced.

As described above, if the present invention is applied, a thin film transistor with a large ON current, a small OFF SE current, a steep rise in the subthreshold region, and excellent reliability can be made without any defects due to plasma damage, etc. It can be manufactured using Further, according to the present invention, there are great advantages in that it is easy to hydrogenate a large-area substrate and mass productivity is also improved.

Applications of the present invention include, for example, a liquid crystal display panel constructed of TPT using non-single crystal silicon as an element material;
Contact type image sensor - A thermal head with a built-in driver, an optical writing element with a built-in driver using an organic EL etc. as a light emitting element, a display element, a three-dimensional IC, etc. can be considered. By using the present invention, these elements can be realized. High performance such as high speed and high resolution will be realized. Further, as described in the embodiments, by applying the present invention to a low temperature process of about 600° C. or lower, it is possible to realize a large-area, high-performance semiconductor device using inexpensive glass as a substrate.

Although FIG. 1 shows an example in which the present invention is applied to a poly-3i TFT manufacturing process, the present invention is not limited to this. It is effective for all insulated gate field effect transistors. The present invention is also effective in transistors in which at least a portion of the channel region is made of microcrystals, and in transistors in which a portion of the channel region is made of an insufficiently hydrogenated amorphous semiconductor formed by sputtering, vapor deposition, etc. It is.

Moreover, even if the channel region is single crystal, three-dimensional IC
When forming an element on a silicon layer that has been recrystallized or grown in a solid phase, defects such as subgrain boundaries are likely to occur within the crystal.
In this case, the characteristics can be effectively improved by terminating the defects using the semiconductor device manufacturing method according to the present invention.

Furthermore, the present invention is also effective for reducing the defect density at the heterojunction interface of HBTs (hetero-bipolar transistors) and the like. In particular, when at least one of the two semiconductor layers forming the Peter junction is made of a non-single crystal semiconductor, the plasma treatment according to the present invention can simultaneously reduce defects in the film and at the interface.

Furthermore, the present invention can be widely applied to semiconductor processes in general, including solar cells, optical sensors, bipolar transistors, and static induction transistors using non-single crystal semiconductors as element materials.

[Effect of the invention] As described above, according to the present invention, poly y −
It is possible to improve the performance of an insulated gate field effect transistor such as a 5i TFT in which at least a portion of the channel region is made of a non-single crystal semiconductor without causing defects due to plasma damage or the like. Further, the present invention can be widely applied not only to insulated gate field effect transistors but also to semiconductor processes in general, and its effects are extremely large.

[Brief explanation of drawings]

FIGS. 1(a) to 1(g) are process diagrams of a thin film transistor in an embodiment of the present invention. FIGS. 2(a) to 2(C) are schematic diagrams of a temperature raising method in an example of the present invention. 1-1; Insulating amorphous material 1-2; Non-single crystal silicon thin film 1-9; Amorphous silicon layer 1-1 o; Cap layer time plane Fig. 2(b)

Claims (5)

[Claims] (1) In a method of manufacturing a semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, a step of forming an amorphous thin film mainly composed of silicon and containing hydrogen; The step of forming a cap layer made of a substance having a hydrogen diffusion coefficient smaller than that of amorphous silicon dioxide on the thin film, and the step of desorbing and diffusing hydrogen present in the amorphous thin film by heat treatment, 1. A method for manufacturing a semiconductor device, characterized in that, in a heat treatment step, a temperature increase rate from a temperature at which hydrogen starts to desorb from amorphous silicon to a predetermined annealing temperature is lower than 5° C./min. (2) The heat treatment temperature in the heat treatment step is 300°C to 500°C.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature is about .degree. (3) The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the amorphous thin film mainly composed of silicon and containing hydrogen is formed by a plasma CVD method. (4) The substrate temperature when forming the amorphous thin film mainly composed of silicon and containing hydrogen by plasma CVD is 200°C.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the amount of damage is less than a certain amount. (5) In a method of manufacturing a semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, a step of forming an amorphous thin film mainly composed of silicon and containing hydrogen; The step of forming a cap layer made of a substance having a hydrogen diffusion coefficient smaller than that of amorphous silicon dioxide on the thin film, and the step of desorbing and diffusing hydrogen present in the amorphous thin film by heat treatment, In the heat treatment process, the temperature is once 400℃~5
1. A method for manufacturing a semiconductor device, comprising at least the steps of raising the temperature to about 00° C. or higher and annealing it, and cooling it to about 400° C. or less and annealing it for a predetermined time.