JPH03250275A - 1 chip microprocessor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention incorporates one or more I10 controllers that operate on a unique processor on the same chip as an LSI equipped with a central processing unit (CPU), and This relates to a one-chip microprocessor system that uses microprograms to control these controllers.

[Conventional technology]

Many methods have been proposed to date to reduce the number of IC chips on the main board and downsize the system device. For example, Japanese Patent Application Laid-open No. 62-107361 rCPU peripheral circuit LS
No. 62: ``A system that promotes the integration of CPU peripheral logic (DMA controller, interrupt controller, interval timer, etc.) into a single chip, such as LS IJ for system configuration, reduces the mounting density on the board, and reduces costs. is disclosed.

In addition, in order to reduce the number of IC chips including the CPU LSI, as shown in Japanese Patent Application Laid-open No. 152001/1988, "Microprocessor J,"
There is a method that incorporates the MA controller to efficiently utilize the hardware. Also, multiple CPs in one chip
JP-A-62-2 which incorporates U and co-processor and operates
No. 95168 "Equipment control device" and JP-A-62-1504
Systems such as No. 59 "Single Chip Microcomputer" have also been proposed.

More recently, as shown in Japanese Unexamined Patent Publication No. 63-41970 r Microcomputer System, a microcomputer that mainly performs arithmetic and data processing functions and a microcomputer that controls peripheral devices are housed on the same chip. A method of reducing the number of IC chips and achieving miniaturization has also been proposed.

[Problem to be solved by the invention]

Furthermore, when controlling complex and highly functional peripheral devices that operate based on advanced computer systems and microprogram control, it is difficult to integrate simple functions into a single chip, which requires a large number of processors. Due to the increase in the number of gates in the LSI, the increase in control memory capacity, or the increase in memory capacity, it becomes impossible to incorporate it into the LSI, and new problems such as bottle necks of control memory interface signals when outputting to the outside of the LSI occur. It is becoming necessary to consider more efficient methods for reducing the number of chips to one chip.

SUMMARY OF THE INVENTION An object of the present invention is to provide a one-chip microprocessor in which a CPU and peripheral I10 are controlled by a microprogram operating only one processor and one microprogram sequencer.

[Means to solve the problem]

The above purpose is to provide engineering and
○ The functions of the controller are realized on the same chip as the CPU, and the I10 controller's unique processor is not used.
This is realized by controlling the CPU by sharing the processor, and by controlling only the microprogram controlled by the microsequencer of the CPU without using a microprogram exclusively for the peripheral I10.

[Effect]

The I10 controller that controls the complex and highly functional peripheral I10 has a general-purpose or dedicated processor and is controlled by a microprogram.
0 The functions of the controller are incorporated into the same chip as the CPU. 1 A part of the control section that originally functions as the CPU is modified,
By directly controlling these I10 control sections, the I10's unique processor can be removed and operated. At the same time, by embedding startup and interrupt processing routines for the I10 control section in a part of the microprogram storage area that controls the CPU, the CPU
If the instruction fetched is an input/output instruction for these ■/○ controllers, the CPU is controlled by branching to the specified processing routine, performing the startup procedure, and then returning to the original CPU instruction processing. Peripheral I10 controller control can be performed without malfunctioning using only a microprogram operating on one microprogram sequencer.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a detailed block diagram of a one-chip processing device showing an embodiment of the present invention. 1 is ALU calculation function, disk controller DKC30, printer controller PR
This is a one-chip microprocessor characterized in that the functions of the C40 are provided on the same chip, and various functions are controlled only by the microprogram of the CPU. Normally, when performing an instruction fetch operation, the operation result of the arithmetic unit ALU13 is stored in the program counter PC8 from the ALU output bus (C bus) 16, the PCB address is sent from the local address 18 to the main memory 5, and the instruction code is sent to the local It is read from the data bus 19 and stored in the instruction register IR6. The instruction code stored in the IR 6 is decoded by the decoder 7, and the address of the microsequencer 2 is switched to branch to the beginning of the specified microprogram.

3 is a ROM/RAM that stores a microprogram, reads data according to the address of the microsequencer 2, stores it in the microdata register EMB4, and stores the data in the EM
The microprogram read to B4 is DKC30.
The DKC 30 and PRC 40 are hardware for controlling the DK device 22 and the printer 23, respectively, and perform a series of controller controls such as controlling the PRC 40 and controlling the ALU 13.
4 and ALU output bus (C bus) 16,
Similar to the control section, data can be freely stored, read, and operated as specified by the microprogram.

The DKC 30 controls the general-purpose LSI HDC 21 and activates the DK device 22. Here, if the logic of the general-purpose LSI HDC 21 can be incorporated into the DKC unit 30 in the LSI, it is also possible to directly control the DK device 22 with the DK control unit 30 in the chip. Also, PRC40 is printer 2
3 is directly controlled and activated.

DK device 22 activated by DKC30-PRC40,
Alternatively, when the operation of the printer 23 is completed, a hardware interrupt is reported to the CPU. There are two methods of reporting: one is in the form of a normal CPU interrupt, and the microprogram that receives the interrupt executes a series of interrupt processing routines, and the other is in the form of a cycle steal process. This method involves interrupting the current program, switching the micro execution address to another program using hardware, and executing the program.

In addition, the aforementioned microprogram storage ROM/RAM
3 stores microprograms for performing these series of controls, and as shown in the memory map 50, the CPU's instruction processing section, interrupt processing, startup routines and analysis processing section for DK and PR are stored. etc. are stored sequentially, and it is possible to execute the control section of any micro address according to the instruction code read from the main memory, and to respond with various processing routines when there is a completion response or interrupt report. It is said that

FIG. 3 is a diagram showing an example of a general connection method between a normal CPU and a peripheral I10 device compared to FIG. 1. C,P
The U60 has a memory 61 for storing microprograms for CPU control, and includes a disk controller DKC62 and a printer controller PRC, which are shown as an example of peripheral equipment/○ equipment.
65 through a common IOC bus 8. DKC6
2 has a dedicated processor 64 and a memory 63 for storing a disk control microprogram, and controls the general-purpose LSI HDC 21 and operates the disk unit [22] under the control of the microprogram. Also PRC65 is DKC62
Similarly, it has a dedicated processor 67 and a memory 66 for storing a printer control microprogram, and operates the printer 23 under microprogram control. Since each DK device 22 or printer 23 can operate under its own microprogram control, after the CPU activates the DKC 62 or PRC 65, the CPU continues processing instructions until a hardware interrupt is reported from the DK device 22 or printer 23. can be executed. However, in this system configuration, the LSI/I
From the viewpoint of reducing the number of C, mounting area, and cost, it is possible to connect multiple peripheral I10 devices to multiple processors,
Control is performed using multiple types of microprograms, and when considering the amount of control ROM/RAM, etc., the implementation efficiency is extremely low.

Furthermore, it also has a CPU 60 and a memory for storing microprograms for controlling the CPU, so a more effective control method is required in order to advance the conversion of the entire system to LSI.

FIG. 2 describes the processing procedure in the one-chip microprocessor shown in FIG. 1.

First, an instruction is fetched from the main memory 5 according to the memory address of the program counter PC8, and an instruction is fetched from the instruction register I.
The instruction code stored in R6 is decoded 100, and if this instruction is not a 0 instruction, the instruction processing 102 of the CPU is directly executed. ■If it is an instruction, the device number is disk controller (DKC) 103.
The microprogram determines whether the activation is for the printer controller (PRC) 104, or other IO, and branches the microaddress to the activation routine 106 for the specified device. When you actually start up the hardware, it immediately returns to the original micro main routine and the CPU
The instruction processing continues 108.

When the IO operation and interrupt processing independent of the cpv instruction operation such as DMA transfer are completed and the end interrupt 109 is returned from the IO, the microprogram starts the interrupt processing 110, and for example, the microprogram starts the interrupt processing 111 from the disk DK. If so, branch the microaddress to the interrupt processing routine 112 of the DK, and if it is an interrupt 113 from the printer PR, branch the microaddress to the interrupt processing routine 114 of the PR.
Performs each interrupt process, immediately returns to the original micro main routine 115 after the analysis is completed, and then
The instruction processing continues 116.

On the other hand, when high-speed interrupt processing is required, processing is performed using the above-described cycle stealing method for activation of an input/output device. Currently executing CPU instruction processing 10
8, by not returning the end interrupt 109 and reporting the cycle steal request 117, the executing microprogram is completely unaware of the interrupt, changes the execution address in hardware, and continues to issue the cycle steal request. 112, 114 The microprogram of the I10 interrupt processing routine that has been executed will be executed. Naturally, the CPU instruction processing that has been executed up to now will be interrupted, and as soon as the 5th interrupt routine 112, 114 ends, 5 The execution address is returned to the steal start address in hardware again without the program being aware of it.

FIG. 4 shows a microprogram switching timing chart. FIG. 4 is a diagram showing, as an example, processing on a time axis according to the procedure for starting up the DK. Both the CPU processing micro and the DK processing micro 200 are controlled by a common micro sequencer 2 within a one-chip microprocessor. The CPU processing micro indicates a micro program group that processes instructions of the CPU, and the I) K processing micro indicates a micro program group that executes DK startup 9 interrupt processing.

The major difference between methods (a) and (b) is shown.

The feature of the (,) method is that the CPU microprogram intervenes in response to an interrupt after the DK is started, and intentionally branches the interrupt to the DK processing micro after a determination process. On the other hand, method (b) is aimed at speeding up interrupt and response processing in the present invention, and the microprogram running the CPU processing unit does not need to be aware of interrupts called cycle steal requests. In this method, the process being executed is interrupted, the micro sequencer is switched to the DK's micro address by hardware, and the DK interrupt process is performed. Therefore, when the interrupt processing is completed, execution is restarted from the CPU processing micro program that was interrupted by the cycle steal, so at this time, the CPU processing micro program is completely unaware and operates in the same sequence as when there was no interrupt. 9 While having the above-mentioned features, as a one-chip microprocessor, even complex and highly functional peripheral I10 can be incorporated on the same chip, and even the process can be carried out using the CPU's microprogram and arithmetic unit. By using this method, it is possible to significantly reduce the ROM/RAM on the system board for storing the ■/○ control microprograms and the general-purpose processor provided exclusively for I10 control, thereby reducing the size of the device. It became possible.

〔Effect of the invention〕

According to the present invention, even in the case of a system having a complex and highly functional peripheral 110, the I1 is installed in the same chip as the CPU.
It is possible to incorporate the 0 controller and control it with the microprogram of the CPU, and the RO for storing the peripheral work/○ LSI on the system board and the control microprogram.
It becomes possible to reduce the number of components such as M/RAM, and it is possible to significantly reduce the size and cost of the device.

In addition, in realizing this method, the number of gates in a chip has increased due to advances in LSI technology, and the number of control ROM/R
Even if the number of peripheral I10s to be included on the same chip as the CPU increases due to the increase in AM capacity, this method can be handled as an extension of the present method, and has the advantage of being expandable in the future.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a central processing unit showing an embodiment of the present invention, FIG. 2 is a diagram showing a processing procedure in the one-chip microprocessor shown in FIG. 1, and FIG. 3 is a diagram showing a conventional example. FIG. 4 is a diagram illustrating a response processing method when accessing the DK. 1... One-chip microprocessor, 2... Micro sequencer, 3... R for microprogram storage
OM/RAM, 4...Micro data register. 5... Main memory, 6... Instruction register, 8... Program counter, 30... Disk controller,
40...Printer controller.゛〜１′ Jth part diagram

Claims (1)

[Claims] 1. In a one-chip microprocessor system that operates under microprogram control, the central processing unit has a dedicated processor, and the control section of the peripheral input/output device that operates under microprogram control is controlled by the central processing unit. A one-chip microprocessor system that is characterized by being incorporated on the same chip as the processing device. 2. It has one or more arithmetic units and controls the central processing unit and one or more peripheral input/output controllers incorporated into the same chip in parallel according to a microprogram running on one microsequencer. A one-chip microprocessor system that is characterized by 3. A control memory for storing microprograms is provided on the same chip or outside the chip, and at least a part of the arithmetic unit, sequencer, and registers in the chip are shared by the central processing unit and the peripheral input/output controller. One-chip microprocessor system. 4. A microcomputer that provides the arithmetic function unit and the control function unit of multiple input/output controllers on the same chip, and stores the instruction processing unit of the central processing unit, interrupt processing, startup routines for input/output devices, termination information analysis routines, etc. A one-chip microprocessor system that is characterized by controlling various input/output functions using programs. 5. Detecting an input/output command for the input/output controller in the chip by decoding the instruction code, branching to the microprocessing for controlling the input/output controller, starting up the peripheral input/output device, and terminating the operation of the peripheral input/output device. Alternatively, when an interrupt request is received from the input/output controller, a cycle steal operation is performed to interrupt the processing of the currently executing microprogram, execute the microprogram for the interrupt processing routine of the peripheral input/output device, and immediately after the analysis is completed. A one-chip microprocessor system that is characterized by restarting suspended microprocessing. 6. Although it operates with only one microsequencer, cycle stealing can be performed on microprograms consisting of multiple tasks that have no mutual relationship and operate independently, without making each microprogram aware of the other. A one-chip microprocessor system that is characterized by changing the execution address.