JPH0325253U - - Google Patents

Info

Publication number
JPH0325253U
JPH0325253U JP1989086593U JP8659389U JPH0325253U JP H0325253 U JPH0325253 U JP H0325253U JP 1989086593 U JP1989086593 U JP 1989086593U JP 8659389 U JP8659389 U JP 8659389U JP H0325253 U JPH0325253 U JP H0325253U
Authority
JP
Japan
Prior art keywords
bare chip
bonding pads
integrated circuit
hybrid integrated
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989086593U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989086593U priority Critical patent/JPH0325253U/ja
Publication of JPH0325253U publication Critical patent/JPH0325253U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本考案の実施例を示す混成集積回路
の要部平面図、第２図は、同混成集積回路におけ
るワイヤボンデイング工程を示す要部縦断側面図
、第３図は、従来例を示す混成集積回路の要部平
面図、第４図は、同混成集積回路におけるワイヤ
ボンデイング工程を示す要部縦断側面図である。 １……回路基板、２……ベアチツプ、３……ボ
ンデイングパツト、３ａ……ボンデイングパツト
の傾斜部、４……絶縁層、５……ワイヤ。 FIG. 1 is a plan view of the main parts of a hybrid integrated circuit showing an embodiment of the present invention, FIG. 2 is a longitudinal cross-sectional side view of the main parts showing the wire bonding process in the hybrid integrated circuit, and FIG. 3 is a conventional example. FIG. 4 is a plan view of a main part of the hybrid integrated circuit shown in FIG. DESCRIPTION OF SYMBOLS 1... Circuit board, 2... Bear chip, 3... Bonding pad, 3a... Inclined part of bonding pad, 4... Insulating layer, 5... Wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 回路基板１の上に搭載されたベアチツプ２と、
回路基板１の上の上記ベアチツプ２の周囲に配置
されたボンデイングパツト３，３…と、上記ベア
チツプ２とボンデイングパツト３，３…とを接続
するワイヤ５とを有する混成集積回路において、
上記ボンデイングパツト３，３…の端の表面が勾
配を有する傾斜部３ａの少なくともベアチツプ２
に近接した部分が絶縁層４で覆われていることを
特徴とする混成集積回路。 A bare chip 2 mounted on a circuit board 1;
A hybrid integrated circuit having bonding pads 3, 3, . . . arranged around the bare chip 2 on the circuit board 1, and wires 5 connecting the bare chip 2 and the bonding pads 3, 3, .
At least the bare chip 2 of the inclined portion 3a has a sloped end surface of the bonding pads 3, 3...
A hybrid integrated circuit characterized in that a portion adjacent to the is covered with an insulating layer 4.
JP1989086593U 1989-07-24 1989-07-24 Pending JPH0325253U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989086593U JPH0325253U (en) 1989-07-24 1989-07-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989086593U JPH0325253U (en) 1989-07-24 1989-07-24

Publications (1)

Publication Number Publication Date
JPH0325253U true JPH0325253U (en) 1991-03-15

Family

ID=31636168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989086593U Pending JPH0325253U (en) 1989-07-24 1989-07-24

Country Status (1)

Country Link
JP (1) JPH0325253U (en)

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