JPH0325592A - Discriminator for money calculator - Google Patents

Abstract

PURPOSE:To perform a discrimination processing with high accuracy by performing the discrimination processing for the sampling data of a storage means on which writing is completed on the storage means selected with first and second switching means sequentially. CONSTITUTION:A first central processing unit 12 writes the sampling data of an object to be counted on memory devices 14a-14c selected with the first switching means 15, and outputs a first control signal when completing the write. Next, the second switching means 13 detects the first control signal, and selects the storage means 14a-14c on which the write with the first central processing unit 12 is completed, and also, outputs a second control signal to instruct the start of the discrimination processing of the object to be counted. A second central processing unit 6 to which the second control signal is supplied performs the discrimination processing of the object to be counted based on the sampling data of the storage means 14a-14c selected with the second switching means 13. In such a way, the discrimination processing can be performed with high accuracy.

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention is applicable to banknotes. li! The present invention relates to a currency counter discriminating device suitable for use in reading and discriminating currency counters.

``Prior Art'' Generally, a money counting machine not only simply counts money, but also reads its image pattern and performs processing to determine whether it is genuine or false.

FIG. 3 is a block diagram showing the configuration of a discriminating device according to the first conventional example of the above-mentioned money counting machine. In this diagram,
This discrimination device includes a sensor 2, an amplifier 3, an A/D converter 4,
CPU (central processing unit) 5, DMA (direct
It consists of a memory access) controller 8 and two memories 9.10. In this discrimination device, one memory 9 is used exclusively for writing sampling data SD, and the other memory IO is used exclusively for discrimination processing.

In the above structure, first, the image pattern of the first counting object is detected by the sensor 2;
The analog signal from is amplified by amplifier 3. Then, the analog signal from the amplifier 3 is sent to the A/D converter 4.
The sampling data of the digital signal S D +
is converted to This sampling data S D + is
It is written into the memory 9 by the CPU 5. When the writing of the sampling data SD is completed, the sampling data SDl written in the memory 9 is transferred by the CPU 5 or the DM controller 8 to the memory IO for discrimination processing. Sampling data SD. Upon completion of the transfer, the CPU 5 performs a determination process based on this sampling data SD. In addition, during the execution of the discrimination process, the sampling data S D t of the second counting object is stored in the memory 9 by the interrupt process of the CPU 5. When the discrimination process is completed, the DMA
Memory 9 to memory 10 by controller/roller 8, etc.
The sampling data S D t is transferred to the host. When the transfer of the sampling data SD2 is completed, the CPU 5 again performs the discrimination process based on the sampling data SD. Thereafter, new sampling data SD3, SD4 supplied from the A/D converter 4
. . . are temporarily stored in the memory 9 for each object to be counted, and then transferred to the memory 10 at a predetermined timing. Then, based on the sampling data SD3, SD4... transferred to this memory 1.0, the CPU
5, the determination process is performed.

Next, a second conventional discrimination device will be explained. The configuration of this discrimination device is similar to the first conventional example shown in FIG. However, in this discriminator, the sampling data S
The writing and determination processing of D l, S D z . . . is performed alternately to the memory 9 and IO.
First, as in the first conventional example, the image pattern of the object to be counted that is sequentially supplied is detected by the sensor 2, and after the analog signal from the sensor 2 is amplified by the amplifier 3, it is sent to the A/D converter 4. The sampling data S D +, S D t', etc. of digital signals are converted. This sampling data SD. , SD1...
* are written alternately to the memory 9 and the memory IO by the DMA controller 8 for each object to be counted. Further, the determination processing by the CPU 5 is performed by the DMA controller 8.
the memory on the opposite side of the memory from which the write is being performed,
That is, the processing is performed sequentially for the memories in which sampling data SD, $D1, . . . have already been written.

"Problem to be Solved by the Invention" By the way, in the first conventional discrimination device shown in FIG.
Memory 9 dedicated to writing to memory 10 dedicated to discrimination processing
It is necessary to transfer sampling data to As a result, the transfer time of sampling data puts pressure on the discrimination processing time, resulting in a problem that it is not possible to perform a high degree of discrimination processing that takes a relatively long processing time and to shorten the sampling interval.

In addition, in the second conventional discrimination device, the CPU and DM
The A controllers share the same common data path. An address bus, etc. is used. Therefore, in reality, the sampling data transfer by the DMA controller and the determination processing by the CPU cannot be processed in parallel; when one of them is operating, the other must be on standby. Further, in general, a program for determination processing includes a large number of instructions related to memory access, and in these instructions, the address of the memory to be accessed is written as a physical address. Therefore, when the memory to be subjected to the determination process is switched, the storage address of the sampling data changes, so that the memory address according to the above instruction and the storage address do not match.

As a result, it is necessary to calculate the memory address according to the above instruction in the program during the determination process. As mentioned above,
With this discrimination device, there is a waiting time because parallel processing cannot be performed, and address calculation is required during the discrimination process. A problem arises in that it becomes impossible to cope with the execution of long and high-level discrimination processing. Further, this discrimination device has a problem in that it cannot respond to a request for an increase in the number of processing objects to be counted and a reduction in the sampling interval due to the above-mentioned reasons.

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a discriminating device for a money counter that can perform highly accurate discriminating processing and shorten the sampling interval.

"Means for Solving the Problem" In order to solve such problems, the present invention includes a plurality of storage means that are set at the same physical address, and a plurality of storage means that are a first switching means for sequentially selecting the storage means for each object to be counted, and writing sampling data for each object to be counted into the storage means selected by the first switching means, and transmitting the first control signal when the writing is completed. sequentially selecting the first central processing unit to output and the storage means for which the first control signal has been detected and writing by the first central processing unit has been completed, and starting a process for determining the object to be counted; a second switching means for outputting a second control signal for instructing; and a determination process based on sampling data of the storage means selected by the second switching means when the second control signal is supplied. It is characterized by comprising a second central processing unit that performs.

"Operation" The first central processing unit writes the sampling data of the object to be counted into the storage device selected by the first switching means. Then, the first central processing unit outputs a first control signal when the above writing is completed. Next, the second switching means detects the first control signal, selects the storage means for which writing has been completed by the first central processing unit, and instructs the start of the counting target object discrimination process. A second control signal is output. The second central processing unit supplied with the second control signal performs a process of determining the object to be counted based on the sampling data of the storage means selected by the second switching means.

"Embodiments" Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this figure ζ, parts corresponding to the parts of the conventional example shown in FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted.

In the figure, 6 is a CPU dedicated to discrimination processing, and a ROM
(Read/Expert/Memory) Discrimination processing and the like are executed according to 7J stored programs. 8 is a RAM (random access memory), which is used as a working area when the CPU 6 executes programs.

Reference numeral 9 denotes peripheral equipment, which includes output means for outputting results of discrimination processing by the CPU 6, and key human power means such as condos.

Next, 1l is an A/D controller, and the sampling start timing for the A/D converter 4. It is designed to control sampling time, etc. [2 is a CPU dedicated to sampling, and the sampling data SD1SD*------ from the A/D converter 4 is stored in the memory 14a. 14b. It is designed to be written to L4c. Further, the A/D controller 1l is configured to issue a write request to the CPU 12 via the data path DB, and the CPU 12 is configured to supply a control signal etc. to inform the controller 11 of the operating state. There is.

Next, 13.15 is a switching circuit, which connects each pair of data path DB I, address bus AB+ and data path DBs address bus AB5 to data path DB2 address bus ABC, data path DB. , address bus AB3, data path DB4, and address bus AB.

In addition, the above-mentioned data path D B t and address bus AB! , data path DB3, address bus A Bs and data path DB. ．． Address bus AB. Each of the memories 14a. 14b and 14c. Furthermore, since the memories 14a, 14b, and 14c are not accessed simultaneously by the CPUs 6 and 12, as will be described later, these memories 14a. 14b. l4c is CP
The same physical address space is set for each of U12 and U6.

16 is a switching controller, and a control signal S.l6 indicates the operating status of each of the CPU 6 and CPU 12.
(first control signal) and control signal S, are supplied. In addition, the switching controller l6
are memory 14a, 14b . 14c, which instructs which one to select, and further outputs a control signal S, ゛ (second control signal) that informs the CPU 6 of the operating state. It has become.

Next, the operation of this embodiment with the above-described configuration will be explained. Here, FIG. 2 is a timing chart for explaining the operation of this embodiment. First, at time t shown in FIG. 2, the image pattern of the first counting object is detected by the sensor 2. Then,
The analog signal from this sensor 2 is amplified by an amplifier 3. The analog signal from this amplifier 3 is the A/D
The converter 4 converts the sampling data S of the digital signal into
D. is converted to And this sampling data S
When D, is detected by the A/D controller 11,
This controller 11 immediately requests the CPU 1 2 to write the sampling data SD r.

When the CPU 12 receives the write request, the CPU 12 determines the time tl''.
"jt, the sampling data SD. supplied from the A/D converter 4 is written into the memory +4a. In this case, the switching circuit 13 has already set the data path DB, address bus A B + to the data by initial setting etc. The CPU 12 connects the sampling data SD.
When writing is completed, the CPU 12 supplies a control signal S to the switching controller I/roller 16. and,
A switching controller l supplied with a control signal S1
6 supplies a control signal S3 to the switching circuit l3. The switching circuit l3 receiving this control signal S3 is
Data path DB, address bus AB. are connected to data path DB3 and address bus AB3. Also, C
PLJ6 sends the control signal S, to the switching controller l
Supply to 6. The switching controller l6 supplied with the control signal S, supplies the control signal S, to the switching circuit l5.

The switching circuit l5 receiving the control signal S4 then switches the data path D B S . Ad1nosbus A B a
Each of the data paths D B ! +Connect to address bus AB. Next, the switching controller l6 c
A control signal St' is supplied to pue to instruct the start of the discrimination process. The CPU 6, which has been supplied with the control signal S, starts a discrimination process based on the sampling data SD, written in the memory 14a from time 1.

Next, at time t, the A/D tells the sensor 2 to detect the physical force of the second object to be counted.
The controller 11 requests the CPU 12 to write the sampling data S D t. C.P.U.I.
2 writes the sampling data SD supplied from the A/l) converter 4 into the memory 14b at times t to t4 upon receiving the write request. When the writing of sampling data SD, ends at time [,, CPU1
2 supplies the switching controller I6 with a control signal S1 indicating the end of writing. Control signal S. The switching controller l6 supplied with this supplies a control signal s3 to the switching circuit l3.

and a switching circuit l to which the control signal S, is supplied.
3 is a data path DBI address bus AB.3 of the CPU 12M). Each of the data path DB. , address bus AB. Connect to.

Next, at time t5, when the discrimination process by the CPU 6 ends, the CPU 6 outputs a control signal S, indicating the end of the discrimination process to the switching controller 16. The switching controller 16 to which this control signal S is supplied
outputs a control signal S, to the switching circuit 15.

And the switching circuit supplied with the control signal S4!
5 connects each of the data path DB s and address bus AB s on the CPUe side to the data path DB. , address bus AB. Connect to. Further, the switching controller I6 supplies the control signal S,' to the CPU 6 to instruct the start of the discrimination process almost at the same time as outputting the control signal S4. Upon receiving the control signal St', the CPU 6 reads the sampling data S D written in the memory 14b.
The determination process starts from time t, based on t.

Then, at time t8, the third object to be counted is 1.
Similarly to the second image, when detected by sensor 2, A/
The D controller 11 requests the CPU 12 to write the sampling data SD. When the CPU 12 receives the write request, from time 76 to t7,
From the A/D converter 4 to IJI. The supplied sampling data S D 3 is written into the memory l4c. When the writing of the sampling data SD3 is completed, the CPUI2 switches to the switching controller! A control signal S1 is output to the terminal 6. The switching controller l6 to which the control signal S is supplied supplies the control signal S3 to the switching circuit l3. The switching circuit l3 to which the control signal S3 is supplied connects the data path DB, address bus A B l
are connected to data path DBt and address bus ABt.

Then, at time t8, when the CPU 6 completes the determination process, the CPU 6 controls the switching controller 16.
A control signal S, indicating the end of the discrimination process, is supplied to the controller. The switching controller 1 to which this control signal S is supplied
6 supplies a control signal S4 to the switching circuit l5. The switching circuit l5 supplied with the control signal S,
Each of the data path DBS and address bus AB on the CPUe side is connected to the data path DB. ．． Address bus AB. Connect to.

Further, the switching controller l6 outputs a control signal S,° to the CPU 6 to instruct the CPU 6 to start the determination process almost at the same time as outputting the control signal S4. Upon receiving the control signal S2', the CPU 6 starts determination processing from time ts based on the sampling data SD written in the memory 14c.

In this way, in the discrimination device according to this embodiment, the sampling data Sp. , SD1... are sequentially stored in the memories 14a, 14b . In parallel with writing to l4c, sampling data SD, SD t...
・Read out and perform discrimination processing. In this case, cpu;+
2, the data paths D B t , D B 3,
D.B. and address buses ABt, AB3, AB. teeth,
It is never shared. Therefore, for the CPUs 6 and 12, there is no waiting time due to mutual processing.

Note that the physical addresses of the memories 14a, 14b, and 14c described above may be set anywhere in the address space of each of the CPU6 and CPU12. Also, memory l 4 a
, I 4 b, 1 4 c is not limited to three, but at least two or more memories may be provided depending on the sampling interval and the like. In addition, in the above-mentioned discrimination device, by setting each memory 14a, 14b, 14c in the same physical address space, even though a plurality of memories are provided, switching between the memories 14a, 14b, 14c Address calculation for discrimination processing is no longer necessary,
This provides an advantage in that the pressure on the discrimination processing time can be reduced. Moreover, in the above-mentioned discrimination device, the sampling processing section for the sampling data SD, SD1, . . . , the sampling data SD. , SD, . . . are functionally independent, so changing the sampling processing section. There is an advantage that the number of memories or the hardware of the discrimination processing section can be easily changed.

"Effects of the Invention" As explained above, according to this invention, No. 1! The first switching means performs the writing of the sampling data of the counting object performed by the central processing unit of the second central processing unit, and the discrimination processing of the sampling data of the storage means that has been written by the first central processing unit, performed by the second central processing unit. By sequentially performing the processing on the storage means selected by the second switching means, it is possible to achieve the advantage of being able to perform high-resistance discrimination processing and shortening the sampling interval.

[Brief explanation of drawings]

No.! The figure is a block diagram showing the structure of an embodiment of this invention.
FIG. 2 is a timing chart for explaining the operation of this embodiment, and FIG. 3 is a block diagram showing the configuration of a conventional discrimination device. 6...CPtJ (second central processing unit), l
2...CPU (first central processing unit),! 3...
... switching circuit (second switching means), 14a,
L4b, 14c...Memory (storage means), l5
......Switching circuit (first switching means), l
6...Switching controller (1st, 2nd
switching means).

Claims (1)

[Claims] a plurality of storage means set to the same physical address; a first switching means for sequentially selecting the plurality of storage means each time a first control signal is supplied; a first central processing unit that writes to the storage means selected by the first switching means and outputs the first control signal when the writing is completed; a second switching means for sequentially selecting the storage means for which writing has been completed by the central processing unit and outputting a second control signal for instructing the start of the counting target object discrimination process; and a second central processing unit that performs a discrimination process based on the sampling data of the storage means selected by the second switching means when a signal is supplied. .