JPH03257547A - Error holding/reading circuit and method - Google Patents

Abstract

PURPOSE:To prevent the breakage of the error contents even if an error reading action is interrupted by providing an error information holding circuit and an error serial reading circuit independently of each other and therefore fetching even such errors that are caused during an error reading action. CONSTITUTION:The error holding circuits 10 - n0 hold the error signal states and output the error state signals 102 - n02 when the errors occur. The error reading circuits 11 - n1 receive the signals 102 - n02, an error read signal 210, and a clock 213, fetch the signals 102 - n02 with the signal 210 set equal to logic '0' and the shift path signals 103 - n03 with the signal 210 set equal to logic '1' respectively at the rising edge of the clock 213, and output the shift path signals 203 - n03 and an error read signal 214. In such a constitution, even such errors that are caused during an error reading action can be fetched and then the error contents are never broken despite the interruption of the error reading action.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to error retention and readout circuits and methods.

[Conventional technology]

Conventionally, information processing devices that serially read error information detected within the information processing device using diagnostic commands, etc. have an error-indicated flip-flop circuit (hereinafter referred to as EIF) for storing error information for each type of error. Normally, the system waits for various error reports to arrive, and when they do, the information is retained, and when an error is read out, all EIFs form a serially connected path so that the error can be read out.

[Problem to be solved by the invention]

In the conventional error holding and reading circuit described above, the operation of capturing and holding errors and the operation of serially reading errors are performed in the same circuit, so errors that occur while reading errors cannot be captured. There is a drawback that there is no

Also, since the EIF is serially connected and errors occur one after another, the contents will be corrupted if the error is read, so it is necessary to loop the serial path to return to the original state.Also, if the error reading is interrupted, the error contents The disadvantage is that it can break.

[Means to solve the problem]

The error holding and reading circuit of the present invention includes a plurality of error holding means for receiving and temporarily storing various error signals, reading and storing the temporarily stored error signals in parallel, and serially reading out the read error signals. and error reading means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

When implemented in an information processing device that holds n pieces of error information and serially reads the error information, the error holding circuits 10, 20, 30 . -, n.

are error signals 101, 201, 301 . -・, n01
and the normal clock 211 are received, and an error occurs -
Error status signal 1 is maintained, and the error status signal 1 is
02,202. ..., n02 are output respectively.

Error reading circuits 11, 21, 31. ..., nl is
Error status signal 102.202.302. ...n02
, an error read signal 210 and a clock 213, and when the error read signal 210 is logic ``0'', the error state signal 102.202302,..., no2 is received, and when the error read signal 210 is logic ``1'', the shift path is Signal 103, 203, 3
03. -, n03 is taken in at the rising edge of the clock 213 and the shift pass signals 203, 303. -, n03
．． Each outputs an error read signal 214.

The clock switching circuit 12 includes a normal clock 211, an error readout clock 212, and an error readout signal 210.
When the error read signal 210 is at logic "O", the normal clock 211 is selected, and when the error read signal 210 is at logic "1", the error read clock 212 is selected and outputted as the clock 213.

Next, the operation of this circuit will be explained.

Error holding circuit 10, 20.30. .-, no are error signals 101, 201, 301 . -・If an error occurs after receiving not, the normal clock signal 211
The data is taken in at the rising edge of , its contents are held, and error state signals 102, 202, 302, . . . , no2 are output.

During normal operation, the error read signal 210 is logic "o"
The normal clock 211 is set by the clock switching circuit 12.
is selected and output as the clock 213. Further, in the error reading circuits 11.21, 31, -nl, the error state signals 102, 202.302, .

During an error read operation, the error read signal 212 is
At logic "1'', the clock switching circuit 12 outputs the error readout clock 212 as the clock 213. Also, the error readout circuit 11゜12.31..., n
1, the shift path signal 103.203. ..., n0
3 is selected as the input and the rising edge of Cook signal 213 causes shift path signals 203, 303 .・ , n
03 and an error read signal 214.

The read data of the error information is transmitted by the error read signal 214, but n 2 clocks 213 are inputted so that all the information is transmitted.

With this configuration, even if an error occurs during the error read operation state, the error holding circuits 10, 20,
30. . . , nO is held in the error read circuits 11, 21, 31 . . . after the error read operation is completed.・・・
. , nl with error status signals 102.202, 302. −
, n02 is input, an error state is entered, and if the error read operation is performed again, it is possible to know the error state.

Also, even if the error read operation is interrupted, the error status signal 1
02,202. . . . Since the information is inputted again by No. 2, the contents are not destroyed, and it is necessary to loop the value and restore it to the original value in order to read the error information using the shift bus, but this is not necessary for the same reason.

〔Effect of the invention〕

As explained above, the present invention has a circuit configuration in which a circuit that holds error information and a circuit that serially reads out errors are provided independently, thereby capturing and reading out errors that occur while reading out errors. This has the effect of making it possible to perform the following operations, and also has the effect that the error contents are not destroyed even if the error reading operation is interrupted, thereby improving the reliability of the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 10.20.30. ~． nO-error holding circuit, 11.
21, 31. ~． nl...Error reading circuit, 12.
... Clock switching circuit, 101, 201, 301, ~.
no1...Error read signal, 102,202.30
2. ~． n02-Error status signal, 103.203,
303. ~． n03- Shift path signal, 210...
Error read signal, 211...Normal clock, 2
12...Error read clock, 213...Clock, 214...Error read signal.

Claims (1)

[Claims] 1. A plurality of error holding means that receive and temporarily store various error signals, and an error readout that reads and stores the temporarily stored error signals in parallel and reads out the read error signals serially. An error holding and reading circuit comprising means. 2. It includes a plurality of error holding means for receiving and temporarily storing various error signals, and an error reading means for reading and storing the temporarily stored error signals in parallel and serially reading out the read error signals. Characteristic error retention and readout method.