JPH03250228A - Circuit and method for holding and reading error - Google Patents

Abstract

PURPOSE:To fetch and read out error generated just in the middle of reading out error by independently providing an error hold circuit to hold various errors and to serially set data, and a circuit to serially read out the errors. CONSTITUTION:Error hold circuits 10, 20, 30...n0 receive error write data 214, error state signals 102-(n-1)02, error signals 101-n01, error write signal 210 and write clock 216. When the error write signal 210 is logic '0', the error signals 101-n01 are fetched and when the error write signal is logic '1', the error write data 214 and the error state signals 102-(n-1)02 are fetched with the starting edge of the write clock 216. Then, the error state signals 102-n02 are outputted respectively. Therefore, in the state of reading out the error, the errors are held in the error hold circuits 10, 20...n0. Thus, the state of error can be known.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to error retention and readout circuits and methods.

[Conventional technology]

Conventionally, the technology for serially reading out error information detected in an information processing device using a diagnostic command, etc. is based on an error index-5f9f1f0f1 circuit (-5f9f1f0f1 circuit) that stores error information.
EIF) for each type of error, and usually waits for various error reports to come in, and when they do, retains that information, and when reading out errors, all EIFs form a serially connected bus and the error can be read out. It was like that.

[Problem to be solved by the invention]

In the conventional error holding and reading circuit described above, the operation of capturing and holding errors and the operation of reading out errors serially are performed in the same circuit, so errors that occur while reading errors cannot be removed. The drawback is that it cannot be loaded.

In addition, since the EIF is connected serially and the error is read out, the contents will be corrupted if the error is read out, so it is necessary to loop the serial bus to return to the original state.Also, if the error reading is interrupted, the error contents will be lost. The drawback is that it can break.

Another disadvantage is that checking the normality of this circuit requires time and effort to generate and check each error.

[Means to solve the problem]

The error holding and reading circuit of the present invention includes an error holding circuit that is capable of holding a plurality of various errors and capable of serially setting data, and a circuit that reads errors serially.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention,
This is an example implemented in an information processing device that holds n pieces of error information and serially reads out the error information.

Error holding circuit 10.20,30. ~． No is error write data 214. Error status signal 102~(n-1)
02 and error signal 101~no1 and error write signal 2
10 and the write clock 216, and when the error write signal 210 is logic "O", the error signals 101 to n
When o1 is logic “1”, error write data signal 2
The 14° error state signals 102 to (n-1)02 are taken in at the rising edge of the write clock 216, and the error state signals 102 to n02 are outputted, respectively.

Further, if an error occurs when the error write signal 210 is at logic "0" and the error signals 101 to no1 rise, the state of the error signal is held.

The error readout circuits 11 to n1 receive the shift bus signal 103.
~nO3, the error status signal 102~nO2, the error read signal 213, and the readout clock 217 are received, and when the error read signal 213 is logic "0", the error status signal 102~n02 is received, and when it is logic "1", the error status signal 102~n02 is received. reads shift bus signals 103-n03 and takes in shift bus signals 203-n03 at the rising edge of clock 217. Each outputs an error read data signal 215.

The error write clock switching circuit 12 receives an error write signal 210, a normal clock 211, and an error write and read clock 212, and when the error write signal 210 is logic "0", the normal clock 211 is switched to logic "1". '', the error write and read clock 212 is output as the write clock 216.

The error read clock switching circuit 13 receives the error read signal 213, the normal clock 211, and the error write and read clock 212, and changes the normal clock 211 to logic "1" when the error read signal 213 is logic "0". is the error write and read clock 21
2 is output as the read clock 217.

Next, the operation of this circuit will be explained.

During normal operation, when the error write signal 210 and the error read signal 213 are both logic "0", the normal clock 211 is selected by the error write clock switching circuit 12 and the error reading clock switching circuit 13, and is used as the write clock 216 and the read clock 217. Normal clock 211 is selected.

And error holding circuit 10.20. ~． nQ and error readout circuits 11, 21 . ~． A normal clock is input to nl. Error holding circuit 10.20,30. ~．
no is the error signal 101201.301. ~． If no1 is selected as the input and an error occurs, the contents are captured at the rising edge of the write clock 216 and the error status signals 102, 202, 302 . ~Output n02.

Error reading circuit 11.21, 31. ~． nl is the error status signal 102, 202 . ~． No. 2 is selected as an input and taken in at the rising edge of the read tally 217.

During the error write operation, the error write signal 210 is logic "1" and the error write and read clock 212 is output as the write clock 216 by the error write clock switching circuit 12.

Further, error holding circuits 10, 20 . ~． If no, error write data signal 214 and error status signal 102,2
02. ~． (n-1)02 is selected as an input and is taken in by the rising edge of the error write clock 216 and the error state signal 102.202. ~． Output n02.

The error information write data is transmitted by the error write data signal, but when zero write clocks 216 are input, all information is set.

During the error read operation, the error read signal 213 is
When the logic is "1", the error read clock switching circuit 13 outputs the error write and read clock 212 as the read clock 217.

Also, error readout circuits 11, 21, 31. ~n1,
Shift bus signals 103, 203. ~.

n03 is selected as input and error read clock 21
The shift bus signal 20 is taken in by the rising edge of 7.
3,303. ~． n03 and error read data signal 2
Outputs 15.

The error information read data is the error read signal 215
The error read clock 217 is transmitted by n
Once entered, all information will be transmitted.

With such a configuration, an error is detected in the error holding circuits 10, 20, . . . during the error read operation state. Since the error reading circuits 11, 21 . ~.

error status signals 102, 202 .nl. ~． n.

2 is input, the error state is captured, and the error read operation is performed again to know the error state.

Also, even if the error read operation is interrupted, the error status signal 1
02,202. ~． Since the information is inputted again by No. 2, the contents are not destroyed, and in order to read the error information by the shift bus, it is originally necessary to loop the value and return it to the original value, but this is not necessary for the same reason.

Also, when checking the normality of this circuit configuration, error signals 101, 201 . ~． Even if no. no. 1 is not output, the error holding circuits 10, 20 . ~
．． It is possible to serially set an error to "no" from the error write data signal 214, and it is also possible to easily check the normality of this circuit configuration.

〔Effect of the invention〕

As explained above, the present invention has a circuit configuration that independently provides an error holding circuit that can hold various errors and set data serially, and a circuit that reads out errors serially. This has the effect of making it possible to capture and compare errors that occur during error reading, and also has the effect that the error contents are not destroyed even if the error reading operation is interrupted, improving the reliability of the device. gets better.

Another advantage is that the normality of this circuit configuration can be easily checked.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 10.20,30. ~． No-・-1 La-holding circuit, 1
1.21, 31. ~． nl...Error reading circuit, 1
2...Error writing clock switching circuit, 13...
Clock switching circuit for error reading, 101. '201.
301. ~． n01--Error signal, 102°202
．． 302. ~． n02--Error status signal, 103.
203.303. ~． n03--Shift bus signal, 2
10...Error write signal, 211...Normal clock, 212...Error write and read clock, 213...Error read signal, 214...Error write data signal, 215...Error read data Signal, 216...Write clock, 217...Read clock.

Claims (1)

[Scope of Claims] 1. It is characterized by comprising an error holding means capable of holding a plurality of various errors and capable of serially setting data, and a means for serially reading out the errors. error retention and readout circuit. 2. An error holding and reading method characterized by comprising an error holding procedure of holding a plurality of various errors and serially setting data, and a procedure of serially reading out the errors.