JPH03292700A - Ram test system - Google Patents

Abstract

PURPOSE:To confirm whether each address of a RAM is correctly operated up to bit units or not by writing ''1'' in bits 0 to 7 independently of one another and testing whether it is correctly read out or not. CONSTITUTION:In the circuit constitution provided with a central processing unit 11, a ROM 12, and a RAM 13, a pattern shifted left bit by bit is written in a memory 13, and this pattern is read out to confirm the coincidence of values. The initial pattern is shifted left by one bit to perform the same test, and this operation is repeated 8 times. Thus, it can be confirmed whether bits 0 to 7 of one address on the RAM 13 are correctly operated independently of one another or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a RAM (read/write memory) test method, and particularly to a RAM operation test method using bit manipulation.

[Conventional technology]

The conventional RAM test method uses an increment pattern (1, 2, 3, 4, etc., in which 1 is added in increments) as a function on the ROM (read-only memory). (See Figure 3, which shows an example of a bit pattern.) After that, the next value was read out from the memory and the written value was compared to see if they matched.

[Problem to be solved by the invention]

Although it is possible to check whether the i, address lines and data lines connected to the RAM are connected correctly using the conventional RAM test method described above, it is possible to check whether each bit of the memory for one address on the RAM operates correctly independently. I have not been able to fully confirm whether this is the case. For example, even if "1" is written to bit 4 of the address in FIG. 3, if it cannot be written, there is a problem that it cannot be found.

[Rounding method to solve the problem]

The RAM test method of the present invention is a first check to confirm the normality of the address line and data line connected to the RAM as a function on the RAM in a circuit configuration including a central processing unit, ROM, and RAM. In order to confirm that each bit of the memory corresponding to each address on the RAM operates correctly, write rlJ independently from bit O to bit 7 and check whether it can be read correctly. It is equipped with a confirmation means.

[Effect]

In the present invention, it is checked whether each address of fl and RAM is operating correctly down to the bit level.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a RAM testing method according to the present invention.

In the figure, 11 is a central processing unit (CPU), 12 is R
OM, 13 is a RAM, and 14 and 15 are address lines and data lines connected to the RAM 13.

In this way, the central processing unit 11, ROMI2 and RA
In the circuit configuration having M13, the functions on the RAM 13 include a means for checking the normality of the address line 14 and the data line 15 connected to the M13 on the RAM 13;
In order to confirm that each bit of the memory corresponding to each address on 3 operates correctly, a means is provided to independently write "1" from bit O to bit T and confirm whether it can be read correctly.

FIG. 2 is an explanatory diagram for explaining the operation of FIG. 1, where (&) indicates the initial value of the bit pattern according to the RAM test method of the present invention, r, (b), and (-) indicate the bit pattern. This figure shows the mode of change.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

First, a central processing unit 11 and a ROM 1 as shown in FIG.
2 and RAMI 3, write a pattern to the memory that shifts one bit to the left as shown in Figure 2 (Hata) (if you shift OX80, it will be 0x0).
1), read this and check whether the values match.

Next, the first pattern is shifted to the left by one bit and a similar test is performed. By repeating this 2 to 8 times (see Figure 2 (b) and (c)), RAMI 3
It can be confirmed that each bit from bits O to 7 operates correctly independently for the above one address.

Here, a pattern in which one particular bit is all 1 (for example, a pattern in which all bits 0 are 1),
The reason why bit 1 is not used the second time and bit 2 is 1 the third time is to make it possible to determine whether what was written to a certain address was correct and whether it was written to that address.

〔Effect of the invention〕

As explained above, the present invention has a central processing unit and a ROM.
With a circuit configuration having a RAM and a RAM, it is possible to confirm whether each address of the RAM is operating correctly down to the bit level.

[Brief explanation of drawings]

gx diagram is a block diagram showing an embodiment of the RAM test method according to the present invention, FIG. 2 is an explanatory diagram for explaining the operation of FIG. 1, and FIG. 3 is a diagram showing an example of the bit pattern of the conventional RAM test method. It is. 11...Central processing unit, 12...ROM. 13...@RAM, 14Φφ...address line, 15.
...Data line.

Claims (1)

[Claims] In a circuit configuration having a central processing unit, ROM, and RAM, the first function on the RAM is to check the normality of the address line and data line connected to the RAM.
In order to confirm that each bit of the memory corresponding to each address on the RAM operates correctly, bits 0 to 7 are independently
A RAM characterized in that it is equipped with a second confirmation means for confirming whether or not the data written in "1" can be read correctly.
Test method.