JPH0330372A - Self arc-extinguishing type power switching device - Google Patents

Abstract

PURPOSE:To enable the three terminal elements to be formed at low cost having no effect of a floating inductance by a method wherein a bipolar transistor, the first MOSFET, the second MOSFET and the third MOSFET are formed on the same chip. CONSTITUTION:The title power switching device is provided with a bipolar transistor 30, the first MOSFET 25 parallel-connected between collector base of the transistor 30 to feed the transistor 30 with base current, the second MOSFET 26 series-connected to the emitter of the transistor 30 as well as the third MOSFET 1 parallel-connected between the base of the transistor 30 and the source of the second MOSFET 25 to extract the base current of the transistor 30 on the same chip. Through these processures, the element cost can be cut down and the floating inductance can be decreased while enabling the three terminal elements to be formed by forming a cascade BiMOS on every one step upward chip.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a self-extinguishing power switching device, particularly a three-terminal self-extinguishing power switching device that is inexpensive and unaffected by stray inductance. Regarding. .

[Prior Art] Conventionally, bipolar junction transistors (hereinafter referred to as BJTs) and MOSFETs have been used as self-extinguishing power switching devices of small to medium capacity.

However, although a BJT can obtain a large current density, its switching speed is slow, resulting in a large switching loss. M.O.S.
Although FETs have high switching speeds, they have problems such as inability to obtain high current densities, especially in devices with high breakdown voltages.

In recent years, in order to compensate for these problems, BJT and MO
Many new elements have been proposed that combine SFETs and the like to enable high-speed, high-current-density switching, and some of them are beginning to be put into practical use.

FIG. 3 is a diagram showing an example of the above-mentioned composite switching element, and shows an element called cascode BiMO8. The operation of this element will be briefly described below.

In FIG. 3, collector terminal 33. An external load is connected between source terminals 36 and a voltage is applied between base terminals 34 .
Connect the base power supply between the source terminals 36 and the gate terminals 3
When a gate voltage is applied to BJT 5 to turn on MOS FET 31, a base current is supplied to BJT 30.

Therefore, B J T is turned on, and emitter current flows through MO3FET 31 to source terminal 36 . On the other hand, if a gate voltage is applied to the gate terminal 35 to turn off MO8FE-r31 from this state, the BJT30
Since the supply of base current is stopped and the emitter becomes open, the BJT 30 shifts to the off state. Generally, when a BJT is on, the base region and the connector region are filled with excess carriers due to conductivity modulation, so the BJT will not be completely turned off until the excess carriers disappear. However, the cascode srMo shown in FIG.
In s, carriers can be pulled away from the base through the low voltage diode 32, so they can be turned off quickly. In addition, since the emitter is open in the off state, the withstand voltage of the BJT30 is not the collector-emitter voltage V (base ratio) but the collector-base voltage V CBO<
Since the emitter is open (emitter open) and the thickness of the collector layer can be reduced, it is possible to achieve a high emitter grounding miniaturization, zero short-circuit forward current amplification factor hfe, and a device with a low on-voltage. .

[Problems to be Solved by the Invention] The above-mentioned conventional tower type switching elements are BJT, M
Because it combines individual elements such as OSFETs and diodes, it is expensive; because it turns off at high speed, stray inductance causes phenomena such as oscillation and false firing, making it difficult to use; and because it is a four-terminal element, it is difficult to use. There was a problem.

The present invention has been made in view of the problems of the prior art described above, and its purpose is to provide a self-extinguishing power switching device of three-terminal element that is inexpensive and unaffected by stray inductance.

[Means for solving the problem] The self-extinguishing power switching device of the present invention has the following features:
On the same chip, a bipolar 1-transistor and a first MOSFET connected in parallel between the collector and base of the transistor to flow the base current of the transistor.
, a second MOSFET connected in series to the emitter of the transistor, and a second MOSFET connected to the base of the transistor to extract the base current of the transistor.
A third MOS F connected in parallel between the sources of E T
It is characterized by the provision of ET.

[Function] According to the present invention, by forming the cascode BiMO8 on one chip, it is possible to reduce element cost and stray inductance, and to achieve three terminals.

That is, the second and third MOSFETs are placed on a bipolar transistor using SoI (Silicon on).

By using the In5ulator technology, a self-extinguishing power switching device can be formed in a single chip at low cost without producing parasitic effects, and stray inductance can be reduced.

Roughly speaking, the first MOSFET is one that allows base current to flow through a bipolar transistor, and this first MOSFET
By forming the drain region of the FET and the collector region of the bipolar transistor in common, conductivity modulation of the train region is generated, thereby causing the first MOS
Although the FET is a high voltage MOSFET,
The MOSFET can have a high current density, and can be configured so that a sufficient base current of a bipolar transistor can flow therethrough. Therefore, a self-extinguishing power switching device with a low on-voltage can be provided.

[Example] The present invention will be roughly described in detail below with reference to Examples shown in the attached drawings.

FIG. 1 is a sectional view showing an embodiment of the present invention. As shown in the figure, a [1-layer 2 with a low impurity concentration is provided on a [I substrate 1] in order to increase the breakdown voltage. n'-layer 2
A p base region 3 formed by partial diffusion is provided on the surface of the substrate.

In the p base region 3, there is n on one side as shown in the figure.
A vine area 8 is formed, which allows N
P N -B J T is configured. Furthermore, within the p base region 3, an n source 6 and a p+ contact region 7 are formed on the other hand.

Then, on the p base region 3 sandwiched between the n+ source 6 and the region in the n− layer 2 in which the p base region vA3 is not diffused, a gate po+y is formed via a gate oxide film 4, as shown in the figure. -si5 are formed, and these lead to n-
Layer 2 and n Vertical MO8FET with substrate 1 as drain
is configured. Further, on the p base region 3, an SO film such as laser annealing or zone melting is applied via the oxide film 9.
3i single crystal film 10 (10-1~1o-s>
is formed.

A gate oxide film 11.1 is formed on this S1 single crystal WAio.
3 through gate po+y-st 1 as shown
2.14 is formed, and this gate Po1y-Si 12
, 14, the source region 10-3 and drain region 10-1, 10-5 are formed.
is formed by self-alignment. Roughly, a silicate glass (hereinafter referred to as PSG) 15 is formed as an interlayer insulating film on this, and on top of this, At-3t wiring 16° 1 for wiring between each region is formed through the opening of the PSG 15.
7 and 18 are formed.

FIG. 2 is an equivalent circuit diagram of the embodiment shown in FIG. 1, and the operation of the element shown in FIG. 1 will be explained using this diagram. In addition,
In FIG. 3, the same parts as in FIG. 1 are given the same reference numerals.

In Figure 2, 30 and 31 are NPN as in Figure 3.
-BJT and nchMO3F
An ET 25 is connected between the collector terminal 21 and the base wiring 18. This MO8FET 25 is a vertical type MO3 in which the n-substrate 1 and the n-layer 2 are double twin in FIG.
Corresponds to a FET, and connects the base current from the collector terminal 21 to B
It has the function of flowing to JT30.

Three terminals are realized by connecting the gate terminal of MO3FET31 and the gate of MO3FET31 to the same potential. On the other hand, a base current handling MO8FET 25 is connected to the base wiring 18, and has the function of drawing out the base current at the time of turn-off, similar to the low voltage diode 32 in FIG. In order to turn on the device shown in FIG. 2, it is sufficient to apply a potential higher than the threshold value of the MO3FET 25, 31 to the gate terminal 19. This results in
When MO8FET31 turns on, the base drive MO
8FET25 is turned on and base current is supplied to BJT30.

This turns on the BJT 30 and its emitter current flows through the MO3FET 31. At this time, the gate threshold of MO8FET25 for handling the base current is the base-emitter voltage of BJ-r30 and MO3FE.
Since it is below the ON voltage of T31, MO3FET 26 is not turned on and the base current to BJT 30 is not bypassed.

On the other hand, in order to turn off the element shown in FIG. 2, it is sufficient to apply a voltage below the threshold value to the gate terminal 19. In other words, when MO3FET25 turns off, BJT3
The supply of base current to 0 is cut off. At the same time, the MO8FET 31 is turned off, so that the emitter of the BJT 30 becomes open and the main current is turned off. B
By turning off JT30, the source terminal 20 of the element
The voltage generated between the BJT 30 and the collector terminal 21 is
is applied to the collector-base junction of , and MO3FET2B. The impedance of the BJT 30 is low at the initial stage of turn-off due to excess carriers due to conductivity modulation, and the voltage between the terminals is applied to the MO3FE-r26. M.O.
Since the gate terminal of 3FET 26 is connected to its train terminal, when the drain voltage rises above the threshold, MO3FET 26 turns on and can draw the base current of BJT 30.

As the turn-off process progresses, the collector-base junction of the BJT30 reversely recovers and has a voltage, so the MO
By designing 3FET26, MO3FET26
It is possible to prevent the element from being destroyed due to high voltage being applied to it.

[Effects of the Invention] As is clear from the above description, according to the present invention, since the cascode and cascade B+MO8 are configured in one chip, it is possible to reduce costs, and the stray inductance due to wiring can be significantly reduced. It is possible to provide an extremely high-speed switching element without excavation, false firing, etc. In addition, MO3F for base drive
By combining ET and BJT, base drive M
o Since the train region of S F E-r can be modulated in conductivity, it is possible to use MO3FE for high voltage base driving.
The current density can be increased despite T, and B
A sufficient base current of the JT can flow, and the on-state voltage can be made sufficiently low. Also, MO for turn-off
By forming the 3'FET' and the base current extraction MO3FET using SOI technology, a cascode and cascade BtvosFE-r can be formed in one chip without any parasitic effects.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of an element showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing an equivalent circuit of the embodiment shown in Fig. 1, and Fig. 3 is an example of a conventional cassette BiMO3. FIG. 1...n substrate, 2...n'' substrate 3...p base region, 4...gate oxide film, 5...
・Gate Po1y-3t, 6...[) Source, 7
...p+ contact region, 8... acid emitter, 9.
...Oxide film, 10...3i single crystal film, 10-1.10
-2.10-3.1(,)-4, 10-5...3i single crystal film, 11...gate oxide film, 12...ge-
1'oiy-3r, 13...gate oxide film, 14.
...Ge-to-P (multi 1y-3i, 15...PSG,
16... Emitter wiring, 17... Source electrode, 1... Base wiring, 19... Gate terminal, 20... Source legitimate child, 21... Collector terminal, 25... MO8F for base drive ET, 26...
MO3FET for base current extraction, 3O-NPN-B
JT, 31-nchMOFE"T, 32...Low voltage diode, 33...]Rector termination, 34...Base terminal, 35...Gate terminal, Fig. 2 Section

Claims (1)

[Claims] (1) A bipolar transistor and a first M connected in parallel between the collector and base of the bipolar transistor.
An OSFET, a second MOSFET connected in series to the emitter of the bipolar transistor, and a third MOSFET connected in parallel between the base of the bipolar transistor and the source terminal of the second MOSFET are formed on the same chip. self-extinguishing power switching device.