JPH0338130A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To decrease the time from out of synchronism in a synchronizing state to a resynchronization state by starting backward protection during forward protection. CONSTITUTION:A synchronizing bit in a data string inputted to an input terminal 1 is detected by a synchronizing bit detection circuit 2 in out of synchronism state, inputted to a storage circuit 6, a value 10 of a binary counter in a pulse generating circuit 5 is stored, and when the value 10 of the binary counter in the case of detecting a synchronization bit is coincident, coincidence information is outputted to a storage circuit 7. When coincidence by backward protection stage number is consecutive, the initial value is set to a pulse generating circuit 5 to cause the synchronization state by the initial value information 12 outputted from the storage circuit 6 and the initial setting pulse 13 outputted from a protection circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous circuit in digital data transmission.

[Conventional technology]

Conventionally, this type of synchronous circuit, as shown in FIG. 2, detects a synchronous bit in a data string input to an input terminal 20 using a synchronous bit detection circuit 21, and generates a pulse generating circuit 24 formed by a binary counter. The coincidence and mismatch detection circuit 22 detects whether or not the frame synchronization pulse 25 matches the frame synchronization pulse 25 outputted from the frame synchronization pulse 25. If the mismatch continues for the number of forward protection stages, an out-of-synchronization state occurs, and then the synchronization bit detection circuit 21
When the synchronization bit is detected in the pulse generation circuit 2, the pulse generation circuit 2
4 is a circuit that is reset by a reset signal 26 from the protection circuit 23 and then enters a synchronized state when the coincidence of the frame synchronization pulse 25 and the synchronization bit continues for the number of rear protective films in the coincidence/mismatch detection circuit 22; It was configured.

[Problem to be solved by the invention]

In the conventional synchronization circuit described above, a mismatch corresponding to the number of forward protection layers is detected and the synchronization goes out of synchronization.The next time a synchronization bit is detected, the pulse generation circuit is reset, and a match corresponding to the number of rear protection films is detected and synchronized. Therefore, if the phase of the data string shifts in the synchronized state, it takes time to resynchronize.

An object of the present invention is to provide a synchronous circuit that solves the above problems.

[Means for Solving the Problem] In order to achieve the above object, a synchronous circuit according to the present invention includes a synchronous bit detection circuit that detects a synchronous bit in an input data string, and an output of the synchronous bit detection circuit. a holding circuit that holds, two protection circuits, a pulse generation circuit formed by a binary counter, and a match between the synchronization bit detected by the synchronization bit detection circuit and the frame synchronization pulse output from the pulse generation circuit. and a coincidence/mismatch detection circuit for detecting mismatch, and the initial value of the pulse generation circuit is set based on the output of the holding circuit and the output of one of the protection circuits.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

In the figure, 2 is a synchronization bit detection circuit, 3 is a coincidence/mismatch detection circuit, 4 and 7 are protection circuits, 5 is a pulse generation circuit, and 6
is a holding circuit.

In the out-of-synchronization state, the synchronization bit in the data string input to the input terminal l is detected by the synchronization bit detection circuit 2. The synchronization bit detected by the synchronization bit detection circuit 2 is
It is input to the holding circuit 6, holds the value 10 of the binary counter in the pulse generation circuit 5, and outputs matching information to the protection circuit 7 when the value 10 of the binary counter matches the next time the synchronization bit is detected. . In this way, when the number of matches continues for the number of rear protective films, the initial value of the pulse generation circuit 5 is set using the initial value information 12 output from the holding circuit 6 and the initial value setting pulse 13 output from the protection circuit 7. It becomes synchronous. In addition, in a synchronized state, if the phase of the data string input to the input terminal l is shifted, the coincidence/mismatch detection circuit 3 detects a mismatch between the synchronization bit and the frame synchronization pulse 8 output from the pulse generation circuit 5. is detected and enters the forward protection state, and at the same time the match/mismatch detection circuit 3
The enable signal 11 is output from the synchronous bit detection circuit 2, the holding circuit 6 becomes enabled, and the value 10 of the binary counter in the pulse generation circuit 5 is held by the synchronous bit newly detected by the synchronous bit detection circuit 2, and then the synchronous bit is detected. When the value IO of the binary counter matches, the protection circuit 7
Output matching information to . In this way, when the number of matches for the number of rear protective films continues and the forward protection of the protection circuit 4 is released, the initial value setting enable signal 9 output from the protection circuit 4 and the initial value output from the holding circuit 6 The initial value of the pulse generation circuit 5 is set using the value information 12 and the initial value setting pulse 13 output from the protection circuit 7, and a synchronized state is achieved.

[Effects of the Invention] As described above, the present invention starts backward protection during forward protection, so it has the effect of shortening the time from the synchronization state to the resynchronization state.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. l...Input terminal 2...Synchronization bit detection circuit 3...Coincidence/mismatch detection circuit 4...Protection circuit 5...
・Pulse generation circuit 6... Holding circuit 7... Protection circuit 8... Frame synchronization pulse 9... Initial value setting enable signal

Claims (1)

[Claims] (1) A pulse generation circuit formed by a synchronous bit detection circuit that detects a synchronous bit in an input data string, a holding circuit that holds the output of the synchronous bit detection circuit, two protection circuits, and a binary counter. and a coincidence/mismatch detection circuit for detecting coincidence or mismatch between the synchronization bit detected by the synchronization bit detection circuit and the frame synchronization pulse output from the pulse generation circuit. A synchronous circuit characterized in that an initial value of the pulse generation circuit is set based on an output of the circuit.