JPH0338634U - - Google Patents
Info
- Publication number
- JPH0338634U JPH0338634U JP9948789U JP9948789U JPH0338634U JP H0338634 U JPH0338634 U JP H0338634U JP 9948789 U JP9948789 U JP 9948789U JP 9948789 U JP9948789 U JP 9948789U JP H0338634 U JPH0338634 U JP H0338634U
- Authority
- JP
- Japan
- Prior art keywords
- film substrate
- bonded
- chip
- conductor wiring
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案にかかるフイルム基板の平面図
、第２図はモールド金型の構造を示す縦断面図、
第３図は本考案に係るフイルム基板のＡ−Ａ′方
向の断面図、第４図は本考案にかかるフイルム基
板のモールド金型との位置を示す平面図。第５図
は従来の技術によるフイルム基板の縦断面図、第
６図は本考案にかかるフイルム基板の実施例の縦
断面図である。
１…フイルム基板、２…導体配線パターン、３
…補強パターン、６…ランナー、７…ゲート、９
…上型、１０…下型、１３…封止樹脂。
FIG. 1 is a plan view of a film substrate according to the present invention, FIG. 2 is a longitudinal sectional view showing the structure of a mold die,
FIG. 3 is a sectional view taken along the line A-A' of the film substrate according to the present invention, and FIG. 4 is a plan view showing the position of the film substrate according to the present invention with respect to a mold. FIG. 5 is a longitudinal sectional view of a film substrate according to the prior art, and FIG. 6 is a longitudinal sectional view of an embodiment of the film substrate according to the present invention. 1...Film board, 2...Conductor wiring pattern, 3
...Reinforcement pattern, 6...Runner, 7...Gate, 9
...Upper mold, 10...Lower mold, 13...Sealing resin.
Claims (1)
ＩＣチツプをボンデイングし、さらに該ＩＣチツ
プをトランスフアーモールトプレスで樹脂封止を
する半導体封止の工程でモールド金型のランナー
、およびゲート部に対応する前記フイルム基板上
の領域に、前記導体配線を構成する部材で補強パ
ターンを形成することを特徴とするフイルム基板
の構造。 In the semiconductor encapsulation process, in which an IC chip is bonded to a film substrate patterned with conductor wiring, and the IC chip is encapsulated with resin using a transfer mold press, the film corresponding to the runner and gate portion of the mold is bonded. A structure of a film substrate, characterized in that a reinforcing pattern is formed in a region on the substrate using members constituting the conductor wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9948789U JPH0338634U (en) | 1989-08-25 | 1989-08-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9948789U JPH0338634U (en) | 1989-08-25 | 1989-08-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0338634U true JPH0338634U (en) | 1991-04-15 |
Family
ID=31648538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9948789U Pending JPH0338634U (en) | 1989-08-25 | 1989-08-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0338634U (en) |
-
1989
- 1989-08-25 JP JP9948789U patent/JPH0338634U/ja active Pending