JPH0487643U - - Google Patents
Info
- Publication number
- JPH0487643U JPH0487643U JP1990130707U JP13070790U JPH0487643U JP H0487643 U JPH0487643 U JP H0487643U JP 1990130707 U JP1990130707 U JP 1990130707U JP 13070790 U JP13070790 U JP 13070790U JP H0487643 U JPH0487643 U JP H0487643U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- semiconductor device
- semiconductor
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
第１図ａは本考案の一実施例による半導体チツ
プの実装部の平面図、第１図ｂは第１図ａのＢ−
Ｂ′線断面図、第２図ａ乃至ｄは本考案の一実施
例による半導体チツプ実装時の充填樹脂の注入過
程図、第３図ａは本考案の他の実施例による半導
体チツプの実装部の平面図、第３図ｂは第３図ａ
のＣ−Ｃ′線断面図、第４図ａは従来例による半
導体チツプの実装部の平面図、第４図ｂは第４図
ａのＡ−Ａ′線断面図、第５図ａ乃至ｃは従来例
による半導体チツプ実装時の充填樹脂の注入過程
図、第６図ａ乃至ｃは従来例による半導体チツプ
実装時の樹脂充填の問題点を説明するための図で
ある。
１……半導体チツプ、２……基板、４……バン
プ、５……充填樹脂、１０，１１……貫通孔。
FIG. 1a is a plan view of a mounting part of a semiconductor chip according to an embodiment of the present invention, and FIG.
A sectional view taken along the line B', FIGS. 2a to 2d are illustrations of the filling resin injection process during semiconductor chip mounting according to one embodiment of the present invention, and FIG. 3a is a mounting part of a semiconductor chip according to another embodiment of the present invention. The plan view of Figure 3b is the same as Figure 3a.
FIG. 4a is a plan view of a conventional semiconductor chip mounting section, FIG. 4b is a sectional view taken along line A-A' of FIG. 4a, and FIGS. 5a to c 6A to 6C are diagrams illustrating the injection process of filling resin when mounting a semiconductor chip according to a conventional example, and FIGS. 1...Semiconductor chip, 2...Substrate, 4...Bump, 5...Filled resin, 10, 11...Through hole.
Claims (1)
とともに、前記半導体チツプと前記基板間を樹脂
充填してなる半導体装置において、 前記基板の前記半導体チツプ実装領域の少なく
とも一部に貫通孔を形成してなることを特徴とす
る半導体装置。[Claims for Utility Model Registration] A semiconductor device in which a semiconductor chip is connected to a substrate via bumps and a resin is filled between the semiconductor chip and the substrate, at least a part of the semiconductor chip mounting area of the substrate. A semiconductor device comprising a through hole formed in the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990130707U JPH0487643U (en) | 1990-11-30 | 1990-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990130707U JPH0487643U (en) | 1990-11-30 | 1990-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0487643U true JPH0487643U (en) | 1992-07-30 |
Family
ID=31878024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990130707U Pending JPH0487643U (en) | 1990-11-30 | 1990-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0487643U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09214071A (en) * | 1996-01-31 | 1997-08-15 | Hitachi Ltd | Control board for household electrical equipment |
| KR100545881B1 (en) * | 1998-03-24 | 2006-01-25 | 세이코 엡슨 가부시키가이샤 | A mounting structure of a semiconductor chip, a liquid crystal device, and an electronic device |
-
1990
- 1990-11-30 JP JP1990130707U patent/JPH0487643U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09214071A (en) * | 1996-01-31 | 1997-08-15 | Hitachi Ltd | Control board for household electrical equipment |
| KR100545881B1 (en) * | 1998-03-24 | 2006-01-25 | 세이코 엡슨 가부시키가이샤 | A mounting structure of a semiconductor chip, a liquid crystal device, and an electronic device |