JPH0339843U - - Google Patents
Info
- Publication number
- JPH0339843U JPH0339843U JP1990000237U JP23790U JPH0339843U JP H0339843 U JPH0339843 U JP H0339843U JP 1990000237 U JP1990000237 U JP 1990000237U JP 23790 U JP23790 U JP 23790U JP H0339843 U JPH0339843 U JP H0339843U
- Authority
- JP
- Japan
- Prior art keywords
- periphery
- plan
- view
- semiconductor
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の第１の実施例の平面図、第２
図は本考案の第２の実施例の平面図、第３図は本
考案の第３の実施例の平面図、第４図は本考案の
第４の実施例の平面図、第５図は本考案の第５の
実施例の平面図、第６図は本考案の第３の実施例
の実装例を示す平面図、第７図は従来の半導体チ
ツプの平面図、第８図は従来の半導体パツケージ
の平面図である。
１……半導体チツプ、２……周辺、３……ボン
デイングパツド、４……内部リード、５……ボン
デイングワイヤ、６ａ……開口部、６ｂ……切り
欠き部、１１……半導体パツケージ、１２……周
辺、１３……外部リード。
Figure 1 is a plan view of the first embodiment of the present invention;
The figure is a plan view of the second embodiment of the present invention, FIG. 3 is a plan view of the third embodiment of the present invention, FIG. 4 is a plan view of the fourth embodiment of the present invention, and FIG. FIG. 6 is a plan view showing a mounting example of the third embodiment of the present invention, FIG. 7 is a plan view of a conventional semiconductor chip, and FIG. 8 is a plan view of a conventional semiconductor chip. FIG. 2 is a plan view of a semiconductor package. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Peripheral, 3... Bonding pad, 4... Internal lead, 5... Bonding wire, 6a... Opening, 6b... Notch, 11... Semiconductor package, 12 ...peripheral, 13...external lead.
Claims (1)
囲まれた内面に開口部を設けるか、または周辺の
一部に凹状の切り欠き部を設けることを特徴とす
る半導体装置。 A semiconductor device characterized in that an opening is provided in the inner surface surrounded by the periphery of a semiconductor chip or a semiconductor package, or a concave cutout is provided in a part of the periphery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990000237U JPH0339843U (en) | 1989-01-10 | 1990-01-06 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP89589 | 1989-01-10 | ||
| JP1990000237U JPH0339843U (en) | 1989-01-10 | 1990-01-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0339843U true JPH0339843U (en) | 1991-04-17 |
Family
ID=31716960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990000237U Pending JPH0339843U (en) | 1989-01-10 | 1990-01-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0339843U (en) |
-
1990
- 1990-01-06 JP JP1990000237U patent/JPH0339843U/ja active Pending