JPH0344424B2 - - Google Patents
Info
- Publication number
- JPH0344424B2 JPH0344424B2 JP60072133A JP7213385A JPH0344424B2 JP H0344424 B2 JPH0344424 B2 JP H0344424B2 JP 60072133 A JP60072133 A JP 60072133A JP 7213385 A JP7213385 A JP 7213385A JP H0344424 B2 JPH0344424 B2 JP H0344424B2
- Authority
- JP
- Japan
- Prior art keywords
- misfet
- type
- source
- conductivity type
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60072133A JPS61230356A (ja) | 1985-04-05 | 1985-04-05 | 半導体集積回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60072133A JPS61230356A (ja) | 1985-04-05 | 1985-04-05 | 半導体集積回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61230356A JPS61230356A (ja) | 1986-10-14 |
| JPH0344424B2 true JPH0344424B2 (de) | 1991-07-05 |
Family
ID=13480486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60072133A Granted JPS61230356A (ja) | 1985-04-05 | 1985-04-05 | 半導体集積回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61230356A (de) |
-
1985
- 1985-04-05 JP JP60072133A patent/JPS61230356A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61230356A (ja) | 1986-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100350575B1 (ko) | 소오스-바디-기판이 접촉된 이중막 실리콘 소자 및 제조방법 | |
| US4300152A (en) | Complementary field-effect transistor integrated circuit device | |
| KR0159451B1 (ko) | 반도체장치의 보호회로 | |
| KR890004472B1 (ko) | Cmos 집적회호 | |
| JPH0821680B2 (ja) | 集積回路 | |
| US4622573A (en) | CMOS contacting structure having degeneratively doped regions for the prevention of latch-up | |
| HK79493A (en) | Integrated circuit of the complementary technique having a substrate bias generator | |
| JPS6050066B2 (ja) | Ｍｏｓ半導体集積回路装置 | |
| Sugino et al. | CMOS latch-up elimination using Schottky barrier PMOS | |
| JP3559075B2 (ja) | Ｃｍｏｓ技術の集積電子回路用の極性反転保護装置 | |
| EP0066429A2 (de) | Halbleiterspeicher | |
| KR100435807B1 (ko) | 정전방전 보호 회로용 반도체 제어 정류기 | |
| US4320409A (en) | Complementary field-effect transistor integrated circuit device | |
| JP3149999B2 (ja) | 半導体入出力保護装置 | |
| EP0708486B1 (de) | Halbleiter-Feldeffekttransistor mit einer grossen Substratkontaktzone | |
| KR940004455B1 (ko) | Cmos 반도체 집적 회로 장치 | |
| JPH044755B2 (de) | ||
| JPH0344424B2 (de) | ||
| EP0121096B1 (de) | Halbleiter-Kontaktstruktur | |
| Cham et al. | Characterization and modeling of the trench surface inversion problem for the trench isolated CMOS technology | |
| KR100842340B1 (ko) | 반도체 집적회로 장치 | |
| JPS6230704B2 (de) | ||
| JP2508826B2 (ja) | 半導体装置 | |
| JP2601664B2 (ja) | 絶縁ゲート型電界効果半導体装置 | |
| JPH03145163A (ja) | サイリスタ |