JPH0346793A - Electric discharge lamp lighting controller - Google Patents

Abstract

PURPOSE:To facilitate the design of a pulse generating circuit without taking changes in constants of a lighting circuit into consideration by setting preset data set by a presettable counter in a setting switch to form a non-overlap interval setting means. CONSTITUTION:When a counter circuit 2 starts to count a clock signal CLK and all outputs Q1-Q12 of the circuit 2 become 'H', a ripple carry signal RCY is output. The signal RCY makes an enable signal ENB to become 'H', and simultaneously, an output pulse signal OUT becomes 'H'. Interval setting data DB1-DB12 are preset at the circuit 2, and the count of the signal CLK is started. Upon the output of the signal RCY, the output pulse signal becomes 'L' while another enable signal ENA becomes 'H'. This operation is repeated. Accordingly, the 'H' and 'L' intervals of the output pulse signal OUT can be arbitrarily set on the basis of the interval setting data DA1-DA12 and DB1-DB12, to set an ON or OFF duty.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a discharge lamp lighting control device for lighting a discharge lamp at high frequency.

[Prior Art] Conventionally, as a discharge lamp lighting control device that lights a discharge lamp at high frequency, a discharge lamp lighting circuit (for example, a half-bridge inverter circuit) that has a pair of switching elements connected in series and lights the discharge lamp at high frequency has been used. ) and a pulse generation circuit that alternately turns on and off both of the above switching elements to form a two-phase clock signal whose on and off duties can be freely set, and a non-overlapping section is provided in the two-phase clock signal. There was something I did.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, the non-overlapping section of the two-phase clock signal was fixed at the circuit design stage. When the various constants of the discharge lamp lighting circuit change due to variations in characteristics, etc., there is a problem in that the setting of the non-overlapping section may become inappropriate and the discharge lamp may not be lit normally.

Therefore, it is necessary to design the circuit with a margin in consideration of changes in the various constants of the discharge lamp lighting circuit, or to change the circuit specifications of the pulse generation circuit in conjunction with changes in the design of the discharge lamp lighting circuit. There was a problem that it became troublesome.

The present invention has been made in view of the above points, and its purpose is to provide a discharge lamp in which the circuit design of the pulse generation circuit can be easily performed without considering changes in the number of rooms in the discharge lamp lighting circuit. An object of the present invention is to provide a lighting control device.

[Means for Solving the Problems] A discharge lamp lighting control device of the present invention includes a discharge lamp lighting circuit that includes a pair of switching elements connected in series and lights a discharge lamp at a high frequency, and a discharge lamp lighting circuit that lights a discharge lamp at high frequency and that alternately turns on both of the switching elements. ,
A discharge lamp lighting control device comprising a pulse generation circuit that forms a two-phase clock signal to be turned off, and providing a non-overlapping section in the two-phase clock signal,
A presettable counter that counts a clock signal and a setting switch that inputs preset data of the presettable counter form a non-overlapping knob section setting means, so that a non-overlapping section is set based on the output of the presettable counter. The pulse generation circuit is configured as follows.

[Function] The present invention is configured as described above, and a discharge lamp lighting circuit including a pair of switching elements connected in series lights a discharge lamp at a high frequency, and also turns both switching elements on and off alternately. In the discharge lamp lighting control device, the non-overlapping section is set in a two-phase clock signal that is output, and the non-overlapping section is set based on the output of a presettable counter that counts the clock signal. Since the non-overlapping section setting means is formed by allowing the preset data to be set to be set using the setting switch, the non-overlapping section can be easily changed using the setting switch, and the number of rooms in the discharge lamp lighting circuit can be changed easily. The circuit design of the pulse generation circuit can now be easily performed without considering changes in the pulse generation circuit.

[Embodiment] FIGS. 1 to 7 show an embodiment of the present invention, in which a two-phase clock O controls on/off a pair of series-connected transistors of a half-bridge discharge lamp lighting circuit 10.
U T 1. The pulse generation circuit forming OUT 2 uses the "H" section setting data and "L" section setting data of the output pulse signal.
``Data latch circuit 1 that latches section setting data;
A presettable counter circuit 2 that counts a clock signal CLK of a constant period and sets the above-mentioned two interval setting data alternately, and a toggle flip-flop circuit 3 that uses a ripple carry signal RCY from the counter circuit 2 as a trigger clock. A pulse width modulated output pulse signal OUT is obtained from the toggle flip-flop circuit 3 by providing a pulse width control means that changes both interval setting data independently. In the embodiment, the pulse width control means is formed by a microprocessor, and the "H" section setting data, "L" section setting data, and data outputted from the microprocessor are input to the input terminal IN of the data latch circuit 1. , ~lNl2, and is latched by a timing signal output from the timing control circuit 4.

Here, the data latch circuit 1 is formed of a primary buffer 1a and a secondary buffer 1b, and both buffers la and lb are as follows.
As shown in Figures 2 and 3, the flip-flop and T
It is formed by a buffer. In the primary buffer 1a,
When the section data set signal HL is input, DT, ~DT input via input terminals IN~IN, □
, 2 are latched as H" section setting data DA, ~DA, 2, and "L" section setting data DB, ~DB, □ by latch signals LATCHA and LATCH8. Also, in the secondary buffer 1b, Latch signal LTC
The latch data DA, ~D of the primary buffer 1a is
A +□, DB, ~DB, □ are taken in, and the section setting data DA, ~DA, □ or DB, ~DB12 selected by the enable signals ENA, ENll are output as the preset data of the counter circuit 2. It has become. Further, the half clock control signal HLF is also latched once and outputted as the signal HALF.

Further, the counter circuit 2 and the toggle flip-flop circuit 3 are integrated as a counter/output circuit 5,
As shown in FIG. 4, a 12-bit counter circuit 2 is formed using three 4-bit presettable counters, and a ripple carry signal RCY of the counter circuit 2 is sent to a toggle flip-flop circuit via a half clock control circuit 6. 3 as a trigger clock signal RCY'. The output of this toggle flip-flop circuit 3 is 2
At the same time, enable signals ENA and EN for reading predetermined preset data from the data latch circuit 1 are output. Here, the half-clock control circuit 6 sets the half-clock control signal HALF to "H".
”, the rise of the ripple carry signal RCY (the inversion timing of the toggle flip-flop circuit) is shifted to the right by half a clock, and the “H” interval and “L” interval are shifted with half a clock precision (double precision) of the clock signal CLK. It is possible to set the interval.

Further, the timing control circuit 4 outputs a latch signal LATCH.
, LATCHA, LATCH, , LTCH as shown in FIG. 5, and a clear signal C.
LEAR, load signal LOAD, latch signal LTC
A counter control circuit 4 as shown in FIG. 6 that generates HI
It outputs a predetermined timing signal based on the clock signal CLK, start signal 5TART, and section data set signal HL output from the microprocessor to control the operation timing of each circuit. There is.

By the way, in the embodiment, the two-phase clock generation circuit 7 that generates the two-phase clock signals OUT + and OUT 2 based on the output pulse signal OUT and the output signal that controls the switching of the discharge lamp lighting circuit 10 are output as output signals. Output pulse signal OUT or output 2-phase clock signal OUT
,,OUT, is output using the switching signal S E/HB.
It is equipped with an output switching circuit 8 that switches between the two, and is a single-end type (single-stone inverter system in which the switching transistor is controlled by the output pulse signal OUT).
Or half-bridge type (2-phase clock signal OUT,
.

A switching control signal for a discharge lamp lighting circuit 10 of a two-stone inverter type in which a pair of switching transistors connected in series is controlled by ou'rz is obtained. Here, the two-phase clock generation circuit 7 includes a presettable counter circuit 7. that counts the clock signal CLK and sets a non-overlapping section. Non-overlapping section setting data is formed by a and a gate control circuit 7b that controls the gate circuit 7C based on the ripple carry signal RCY2' output from the presettable counter circuit 7a, and is set by an 8-bit setting switch. Two-phase clock signals OUT, OUT, in which non-overlapping sections are set based on HB, -HB, are output.

The operation of the embodiment will be explained below using the time charts shown in FIGS. 8 and 9. FIG. 8 is a waveform diagram showing the basic operation of this embodiment. First, when the start signal 5TART output from the microprocessor rises, the system reset is performed. When A + 2 is determined, the section data setting signal HL rises from the microprocessor, one pulse of the latch signal LATCHA is output, and IT Hl + section setting data DA, ~D A + z are stored in the primary buffer 1a of the data latch circuit 1. Next, when the 'L' section setting data DB, ~DB+z to be latched is determined, the latch signal L is set at the falling edge of the section data setting signal HL.
One pulse of ATCHI is output, and the "L" section setting data D B + to D B lz are latched into the primary buffer 1 a of the data latch circuit 1 .

Next, the clear signal CLEAR becomes "L", one pulse of the latch signal LTCH is output, and both section setting data D
A + ~D A + z, DB, ~DB, 2 are latched into the secondary buffer 1b. At this time, enable signal E
Since NA is "H", data is sent from the secondary buffer 1b.
When the H" section setting data DA, ~D A + 2 is read out and the load signal LOAD for setting preset data in the counter circuit 2 is output, the "H" section setting data DAI-DA, 2 is output to the counter circuit 2. is set. In this state, the clock signal CLK by the counter circuit 2 is set.
starts counting, and the outputs Q, ~Q of the counter circuit 2
2 all become “H”, the ripple carry signal RCY
is output. The enable signal EN becomes "H" by this ripple carry signal RCY, and at the same time the output pulse signal OUT also becomes "H". Then, the section setting data DB, ~D B + 2 are preset in the counter circuit 2, and the clock When the count of the signal CLK is started and the ripple carry signal RCY is obtained, the output pulse signal becomes "L" and the enable signal ENA becomes "H".
” and the above operation is repeated.

Therefore, both section setting data DAI~DA+2
, DB+~DB,2 based on the output pulse signal OU
The "H-section" and "L" section of T can be set arbitrarily (within a range of 12 pits), and on and off duties can be set. In addition, when changing the on/off duty, "H" section setting data DA, ~DA
+2, set the section data setting signal HL to “H”.
”, “L” section setting data DB, ~DB + 2
After setting , the section data setting signal HL may be set to "L".

For example, as shown in FIG.
When setting the “section” to 161 pulses and the “L” section to 164 pulses, the “H” section setting data DA, ~DA,
Set the 8th and 6th bits of 2 to "1",
L” section setting data DB, ... DB, 8th bit of □,
It is sufficient to set the 6th bit, 2nd bit, and 1st bit to "1". In this case, the output pulse signal OUT
The period is 20.2 μsec, which corresponds to 325 pulses of the clock signal CLK, and the frequency is 49°2 kHz. Furthermore, if the width of the "H" section or "L" section is widened by one pulse (62.5 nsec), the period will be 326 pulses of the clock signal CLK, and the frequency will be 49.
．． It becomes 1kHz. Therefore, in the embodiment, the "H" section or "L" section of the output pulse signal OUT is set to 62.
It can be set in 5nsec increments, and the frequency can be controlled in 0.1kHz increments, and the setting accuracy is as follows:
This is a setting accuracy that cannot be achieved with a discharge lamp lighting control device that uses a software internal counter using a microprocessor, and when used as a switching control signal for a discharge lamp lighting control device, fine-grained lighting control can be performed. .

It goes without saying that setting accuracy can be further increased by increasing the frequency of the clock signal CLK counted by the counter circuit 2.

Next, FIG. 9 is an explanatory diagram of the operation of half clock control, where the half clock control signal HLF output from the microcomputer (that is, the signal HALF output from the data latch circuit 1) is "L". for,
Ripple carry signal RCY is toggled as is 7971
This becomes the trigger clock for the 7071 circuit 3, as shown in Figure 9(b).
As shown in FIG. 2, the output pulse signal OUT is inverted in synchronization with the rise of the ripple carry signal RCY.

- On the other hand, when the half clock control signal HLF becomes "H", the ripple carry signal R
The rising edge of CY is shifted to the right by half a clock, and this shifted pull-carry signal RCY' is toggled 7.
This serves as a trigger clock for the 9717071 circuit 3 and performs an inversion operation of the output pulse signal OUT. Therefore, when the half clock control signal HLF is "H", the "H" interval or the "L" interval is determined by the interval setting data D A + ~
D A + 2.

Figure 9 (b
), it can be made wider by half a clock of the clock signal CLK, the setting accuracy of the H'' interval and the IIIL11 interval can be doubled without increasing the frequency of the clock signal CLK, and inexpensive circuit elements can be used. This makes it possible to reduce costs.Also,
Half clock control signal HLF is set as interval data setting signal H
By synchronizing with L, half clock control can be performed automatically.

That is, the section setting data DA, ~DA + z,
By inputting the half clock control signal HLF when inputting D B to D B +2, the frequency f of the output pulse signal OUT is changed at regular intervals to dim the discharge lamp in steps and perform a soft start. is now possible. Fig. 10(a) shows an example of the change in frequency f when lighting a discharge lamp is soft-started without performing half-clock IIIJII, and Fig. 10(b) shows the frequency when soft-starting the lighting of a discharge lamp using half-clock control. An example of a change in f is shown. When half-clock control is performed, the width of change in frequency f can be halved compared to when half-clock control is not performed, and smooth soft start can be achieved by fine-grained stepwise dimming. It turns out that it can be done.

Next, in the two-phase clock generation circuit 7, a clock signal CLK is output from a presettable counter circuit 7a to which non-overlap section setting data HB, ~HB.
As shown in FIG. 11, the ripple carry signal R output from the presettable counter circuit 7a
A gate control signal for controlling the gate circuit 7C is formed based on CY2°, and the gate circuit 7C controlled by the gate control signal provides a two-phase clock signal OUT with a non-overlapping section added to the output pulse signal OUT.
OUT is formed.

The output pulse signal OUT and the two-phase clock signals OUT + and OUT 2 generated as described above are outputted via the output switching circuit 8, and the output switching signal S E/HB is H”, the output pulse signal OUT is output and the output switching signal S
When E/HB is “L”, two-phase clock signal OUT
+, OUT 2 is output. Therefore, by appropriately setting the output switching signal SE/HB, it is possible to obtain a discharge lamp lighting control device that is compatible with a single-end type or half-bridge type discharge lamp lighting circuit 10.

[Effect 1 of the Invention] The present invention is configured as described above, and a discharge lamp lighting circuit including a pair of switching elements connected in series lights a discharge lamp at a high frequency, and both switching elements are turned on alternately. In a discharge lamp lighting control device in which a non-overlapping section is provided for a two-phase clock signal that is turned off, the non-overlapping section is set based on the output of a presettable counter that counts the clock signal, and the non-overlapping section is set in the presettable counter. Since the non-overlapping section setting means is formed by allowing the preset data to be set using the setting switch, the non-overlapping section can be easily changed using the setting switch, and various constants of the discharge lamp lighting circuit can be changed. This has the effect that the circuit design of the pulse generation circuit can be easily performed without considering the above.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIGS. 2 to 7 are circuit diagrams of the main parts of the same, and FIGS. 8 to 11 are operation explanatory diagrams of the same. 1 is a data latch circuit, 2 is a counter circuit, 3 is a toggle flip-flop circuit, 4 is a timing control circuit, 7 is a two-phase clock generation circuit, and 8 is an output switching circuit.

Claims (1)

[Claims] (1) Consisting of a discharge lamp lighting circuit that includes a pair of switching elements connected in series and lights the discharge lamp at high frequency, and a pulse generation circuit that forms a two-phase clock signal that turns both switching elements on and off alternately. In the discharge lamp lighting control device in which the two-phase clock signal has a non-overlapping section, a presettable counter that counts the clock signal and a setting switch that inputs preset data of the presettable counter have a non-overlapping section. 1. A discharge lamp lighting control device, characterized in that a pulse generation circuit is configured to form a section setting means and set a non-overlapping section based on the output of the presettable counter.