JPH0346794A - Electric discharge lamp lighting controller - Google Patents

Abstract

PURPOSE:To facilitate the design of circuits by selectively outputting a pulse signal for controlling a switching element of a single end type electric discharge lamp lighting circuit, and two-phase clock signals for controlling a switching element of a half bridge type electric discharge lamp lighting circuit. CONSTITUTION:A first pulse generating circuit for outputting a pulse signal for controlling the switching element of a single ene type electric discharge lamp lighting circuit 10 receives an output pulse signal OUT modulated in its pulse width from a toggle FF circuit via a pulse width controller. A two- phase clock generating circuit 7 forms two-phase clock signals OUT1, OUT2, where a non-overlap interval is applied to the output pulse signal OUT by a gate circuit. The output pulse signal OUT and the two-phase clock signals OUT1, OUT2 are output via an output switching circuit 8. When an output switching signal SE/HB is 'H', the output pulse signal OUT is output. Meanwhile, when the signal SE/HB is 'L', the two-phase clock signals OUT1, OUT2 are output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a discharge lamp lighting control device for lighting a discharge lamp at high frequency.

[Prior Art] Conventionally, a discharge lamp lighting control device for lighting a discharge lamp at high frequency has been equipped with a single-ended discharge lamp lighting circuit consisting of an inverter circuit formed using one switching element. There are two types of discharge lamps: one that lights up the lamp, and one that is equipped with a half-bridge discharge lamp lighting circuit consisting of an inverter circuit formed using a pair of switching elements connected in series, and that lights the discharge lamp at a high frequency. Ta.

In a discharge lamp lighting device using a single-ended discharge lamp lighting circuit, dimming is performed by controlling the on and off of a switching element made of a transistor using a pulse width modulated pulse signal. In a half-bridge discharge lamp lighting device, dimming is performed by controlling both switching elements with a two-phase clock signal (provided with a non-overlapping section).

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, the switching control circuits corresponding to the winter-type discharge lamp lighting circuits were designed in separate design rooms, which made circuit design troublesome. However, there was a problem that the mass production effect was reduced and the cost increased.

The present invention has been made in view of the above points, and its purpose is to provide a discharge lamp lighting control device that allows easy circuit design and reduces costs through mass production. .

[Means for Solving the Problems] A discharge lamp lighting control device of the present invention includes a first pulse generation circuit that outputs a pulse width modulated pulse signal that controls a switching element of a single-ended discharge lamp lighting circuit;
A second pulse generation circuit outputs a two-phase clock signal that alternately turns on and off a pair of series-connected switching elements of a half-bridge discharge lamp lighting circuit, and the signals output from both pulse circuits are appropriately selected. The output switching circuit is equipped with an output switching circuit for outputting the output.

[Function] The present invention is configured as described above, and includes a pulse signal that controls a switching element of a single-ended discharge lamp lighting circuit, and a pulse signal that controls a pair of switching elements of a half-bridge discharge lamp lighting circuit. Since the phase clock signal is appropriately selected and outputted, and the switching control circuit can be shared, circuit design can be simplified, and costs can be reduced due to the mass production effect.

[Embodiment] FIG. 1 shows an embodiment of the present invention, in which a first pulse generation circuit that outputs a pulse signal for controlling a switching element of a single-ended discharge lamp lighting circuit 10 has a first pulse generation circuit that outputs a pulse signal for controlling a switching element of a single-ended discharge lamp lighting circuit 10. A data latch circuit 1 that latches H" interval setting data and "L" interval setting data, a presettable counter circuit 2 that counts a constant cycle clock signal CLK, and sets both of the above interval setting data alternately; Ripple carry signal RC from counter circuit 2
The pulse width modulated output pulse signal OUT from the toggle flip-flop circuit 3 is composed of a toggle flip-flop circuit 3 that uses Y as a trigger clock, and is provided with a pulse width control means that changes both interval setting data independently. I'm trying to get it. In the embodiment, the pulse width control means is formed by a microprocessor, and the "H" interval setting data and "HI" interval setting data outputted from the microprocessor are input to the input terminal IN of the data latch circuit 1. I-I N + 2 is input,
It is designed to be latched by a timing signal output from the timing control circuit 4.

Here, the data latch circuit 1 is formed of a primary buffer 1a and a secondary buffer 1b, and both buffers la and lb are as follows.
As shown in Figures 2 and 3, the flip-flop and T
It is formed by a buffer. In the primary buffer 1a,
When the section data set signal HL is input, the input terminal IN.

~IN, DT input via □, ~D T + 2
is set to “H” by the latch signals LATCHA and LATCH.
``Section setting data DA +~DA 12, ``L'' section setting data DB, ~DB, 2 are latched.In addition, in the secondary buffer 1b, the latch signal LTCH causes the latching of the primary buffer 1a. Latch data D
A counter circuit takes in A + ~ D A + 2, DB, ~ D B +□, and converts the section setting data DAI ~ D A +□ or DB, ~ DB1□ selected by the enable signals ENA and E Na to the counter circuit. It is designed to be output as preset data of 2. In addition, the half clock control signal HLF is also latched once and the signal HALF is
It is designed to be output as .

Further, the counter circuit 2 and the toggle flip-flop circuit 3 are integrated as a counter/output circuit 5,
As shown in FIG. 4, a 12-bit counter circuit 2 is formed using three 4-bit presettable counters, and a ripple carry signal RCY of the counter circuit 2 is sent to a toggle flip-flop circuit via a half clock control circuit 6. 3 as a trigger clock signal. The flip-flop output of this toggle flip-flop circuit 3 is outputted as an output pulse signal OUT via two inverters, and at the same time, enable signals ENA and E for reading predetermined preset data from the data latch circuit 1 are output.
Here, the half clock control circuit 6 outputs the half clock control signal HALF.
is "H", the rising edge of the ripple carry signal RCY (the inversion timing of the toggle flip-flop circuit) is shifted to the right by half a clock, and the clock signal CL
"H" interval, "L'" with half clock precision (double precision) of K
″It is possible to set the interval.

Further, the timing control circuit 4 outputs a latch signal LATCH.
, LATCHA, LATCH, , LTCH as shown in FIG. 5, and a clear signal C.
LEAR, o-do signal LOAD, latch signal LTCH,
The counter control circuit 4b as shown in FIG. , to control the operation timing of each circuit.

On the other hand, a two-phase clock signal OUT controlling a pair of switching elements of the half-bridge discharge lamp lighting circuit 10
1. The second pulse generation circuit that outputs OUT 2 is formed of a two-phase clock generation circuit 7 that generates two-phase clock signals OUT + and OUT t based on the output pulse signal OUT.

Further, as an output signal for controlling switching of the discharge lamp lighting circuit 10, an output pulse signal OUT may be output, or an output pulse signal OUT may be output.
Whether the phase clock signals OUT+ and 0UT2 are output is determined by the switching signal S E/ set by the changeover switch.
Switching is performed by an output switching circuit 8 that is switched by HB, and a switching control signal for a single-ended or half-bridge discharge lamp lighting circuit 10 can be obtained. Here, the two-phase clock generation circuit 7 includes a presettable counter circuit 7a that counts the clock signal CLK and sets a non-overlapping period, and a gate based on the ripple carry signal RCY2° output from the presettable counter circuit 7a. A two-phase clock signal in which a non-overlap section is set based on non-overlap section setting data HB, -, -HBI, which is formed by a gate control circuit 7b that controls a circuit 7C and is set by an 8-bit setting switch. OU
It is designed to output T++ OUT.

The operation of the embodiment will be explained below using the time charts shown in FIGS. 8 and 9. FIG. 8 is a waveform diagram showing the basic operation of this embodiment. First, when the start signal 5TART output from the microprocessor rises, the "H" section setting data DA1 to DA , 2 are determined, the section data setting signal HL rises from the microprocessor, one pulse of the latch signal LATCHA is output, and the "H" section setting data DA is sent to the primary buffer 1a of the data latch circuit 1.
, ~DA, □ are latched 0 Next, when the "L" section setting data DB, ~DB, , are determined, one pulse of the latch signal LATCHa is output at the falling edge of the section data setting signal HL, and it becomes "L". Section setting data DB + ~ DB,
2 is latched into the primary buffer 1a of the data latch circuit 1.

Next, the clear signal CLEAR becomes "L", one pulse of the latch signal LTCH is output, and both interval setting data DA
, ~DA+2, DB, ~D B +2 are latched into the secondary buffer 1b. At this time, the enable signal ENA
Since IJC is “H”, “H” section setting data DA, ~DAI□ are read from the secondary buffer 1b,
When the load signal LOAD for setting preset data to the counter circuit 2 is output, the counter circuit 2 outputs “H”.
"Section setting data DA + ~ DA, □ is set. In this state, the clock signal CLK by the counter circuit 2
starts counting, and the outputs Q, ~Q of the counter circuit 2
When all 12 become “H”, the ripple carry signal RC
Y is output. The enable signal EN becomes "H" by this ripple carry signal RCY, and the output pulse signal OUT also becomes "H" at the same time. Then, the section setting data DB, ~DB,, etc. are preset in the counter circuit 2, and the clock signal When the CLK count starts and the ripple carry signal RCY is obtained, the output pulse signal becomes "L" and the enable signal ENA becomes ``H''.
, and the above operation is repeated.

Therefore, both section setting data D A + ~ D A +
2. The 'H' and 'L' sections of the output pulse signal OUT can be arbitrarily set (within a 12-bit t! range) based on DB+~DB, and the on/off duty can be set. In addition, when changing the on/off duty, "H" section setting data DA, ~D
After setting A + 2, section data setting signal HL
is set to “H” and “L” section setting data DB + ~ DB
, □, then set the section data setting signal HL to “L”
You should do it.

For example, as shown in FIG. 8, the frequency of the clock signal CLK is 16 MHz (period 62.5 nsec)
When setting the “section” to 161 pulses and the “L” section to 164 pulses, the “H” section setting data DAI to D A
Set the 8th and 6th bits of l2 to 1'',
It is sufficient to set the 8th bit, 6th bit, 2nd bit, and 1st bit of the "L" section setting data DB, ~DB+2 to 1". In this case, the output pulse signal O
The period of UT is 325 pulses of clock signal CLK, which is 20.2 μsec, and the frequency is 49°2kHz.
becomes. Also, set the width of the 'H' section or 'L' section to 1
If it is widened by the pulse amount (62.5 nsec), the period becomes 326 pulses of the tarok signal CLK, and the frequency becomes 49.1 kHz. Therefore, in the embodiment, the H" interval or the "L" interval of the output pulse signal OUT is set to 62
Can be set in 5nsec increments, and can be set in 0.1kH2
This means that the frequency can be controlled in increments, and this setting accuracy cannot be achieved with a discharge lamp lighting control device that uses a software internal counter using a microprocessor. When used, detailed lighting control can be performed.

It goes without saying that setting accuracy can be further increased by increasing the frequency of the clock signal CLK counted by the counter circuit 2.

Next, FIG. 9 is an explanatory diagram of the operation of half clock control, where the half clock control signal HLF output from the microcomputer (that is, the signal HALF output from the data latch circuit 1) is "L". for,
The ripple carry signal RCY directly becomes the trigger clock for the toggle flip-flop circuit 3, as shown in FIG. 9(b).
As shown in FIG. 2, the output pulse signal OUT is inverted in synchronization with the rise of the ripple carry signal RCY.

- On the other hand, when the half clock control signal HLF becomes H'',
As shown in FIG. 9(a), the ripple carry signal RC
The rising edge of Y is shifted to the right by half a clock, and this shifted pull-carry signal RCY becomes a trigger clock for the toggle flip-flop circuit 3, and the output pulse signal OUT is inverted. Therefore, when the half clock control signal HLF is "H", the "H" section or the L" section is set as the section setting data D A + ~ DA
, □.

D The setting accuracy of the "L" section can be doubled and inexpensive circuit elements can be used, making it possible to reduce costs.Also, the half clock control signal HLF can be synchronized with the section data setting signal HL. By doing so, half clock control can be performed automatically.

That is, the section setting data DAI~DA+2,
By inputting the half clock control signal HLF when inputting D B + to D B + 2, the frequency f of the output pulse signal OUT is changed at regular intervals to dim the discharge lamp in steps and soft start it. It is now possible to do so. Figure 10 (a) shows an example of the change in frequency f when lighting a discharge lamp is soft-started without performing half-clock control, and Figure 10 (b) shows an example of how the frequency f changes when soft-starting a discharge lamp using barf clock control. An example of a change in frequency f is shown. When half-clock control is performed, the width of change in frequency f can be halved compared to when half-clock control is not performed. You can see that you can start.

Next, in the two-phase clock generation circuit 7, a clock signal CLK is output from a presettable counter circuit 7a to which non-overlap interval setting data HB, ~HB are preset.
As shown in FIG. 11, the ripple carry signal R output from the presettable counter circuit 7a
A gate control signal for controlling the gate circuit 7c is formed based on CY,', and the gate circuit 7C controlled by this gate control signal generates a two-phase clock signal OUT+ in which a non-overlapping section is added to the output pulse signal OUT.
0UT2 is formed.

Output pulse signal OUT and two-phase clock signal OUT generated as described above 1. OUT 2 is
It is designed to be output via the output switching circuit 8, and when the output switching signal SE/HB is "H", the output pulse signal OUT is output, and the output switching signal S
When E/HB is “Yes”, two-phase clock signal OUT
+, OUT 2 is output. Therefore, by appropriately setting the output switching signal SE/HB, it is possible to obtain a discharge lamp lighting control device that is compatible with a single-end type or half-bridge type discharge lamp lighting circuit 10.

[Effects of the Invention] The present invention is configured as described above, and includes a pulse signal that controls a switching element of a single-ended discharge lamp lighting circuit, and a pulse signal that controls a pair of switching elements of a half-bridge discharge lamp lighting circuit. Since the phase clock signal is appropriately selected and outputted, and the switching control circuit can be shared, circuit design can be simplified, and costs can be reduced through mass production.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIGS. 2 to 7 are circuit diagrams of the main parts of the same, and FIGS. 8 to 11 are operation explanatory diagrams of the same. 1 is a data latch circuit, 2 is a counter circuit, 3 is a toggle flip-flop circuit, 4 is a timing control circuit, 7 is a two-phase clock generation circuit, 8 is an output switching circuit, and 10 is a discharge lamp lighting circuit.

Claims (1)

[Claims] (1) A first pulse generation circuit that outputs a pulse width modulated pulse signal that controls the switching elements of the single-ended discharge lamp lighting circuit, and a pair of series-connected switching elements of the half-bridge discharge lamp lighting circuit. A second pulse generation circuit that outputs a two-phase clock signal that alternately turns on and off, and an output switching circuit that appropriately selects and outputs the signals output from both pulse circuits. Light lighting control device.