JPH0348534B2 - - Google Patents
Info
- Publication number
- JPH0348534B2 JPH0348534B2 JP6007983A JP6007983A JPH0348534B2 JP H0348534 B2 JPH0348534 B2 JP H0348534B2 JP 6007983 A JP6007983 A JP 6007983A JP 6007983 A JP6007983 A JP 6007983A JP H0348534 B2 JPH0348534 B2 JP H0348534B2
- Authority
- JP
- Japan
- Prior art keywords
- carry
- circuit
- look
- ahead
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6007983A JPS59186042A (ja) | 1983-04-07 | 1983-04-07 | 桁上げ先見回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6007983A JPS59186042A (ja) | 1983-04-07 | 1983-04-07 | 桁上げ先見回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59186042A JPS59186042A (ja) | 1984-10-22 |
| JPH0348534B2 true JPH0348534B2 (de) | 1991-07-24 |
Family
ID=13131720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6007983A Granted JPS59186042A (ja) | 1983-04-07 | 1983-04-07 | 桁上げ先見回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59186042A (de) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61240330A (ja) * | 1985-04-18 | 1986-10-25 | Toshiba Corp | 加算回路 |
-
1983
- 1983-04-07 JP JP6007983A patent/JPS59186042A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59186042A (ja) | 1984-10-22 |
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