JPH0350253U - - Google Patents

Info

Publication number
JPH0350253U
JPH0350253U JP10967989U JP10967989U JPH0350253U JP H0350253 U JPH0350253 U JP H0350253U JP 10967989 U JP10967989 U JP 10967989U JP 10967989 U JP10967989 U JP 10967989U JP H0350253 U JPH0350253 U JP H0350253U
Authority
JP
Japan
Prior art keywords
memory
trace
data
function
tracing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10967989U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10967989U priority Critical patent/JPH0350253U/ja
Publication of JPH0350253U publication Critical patent/JPH0350253U/ja
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

図は本考案の一実施例によるトレース機能をパ
リテイエラー検出までのプログラムトレース用と
して動作させた時のハードウエアブロツク図であ
る。 1……CPU、2……メモリ制御部、3……メ
モリ、4……アドレスバス、5……データバス、
6……パリテイ検出信号、7……トレース制御部
、8……アドレストレース用メモリ、9……デー
タトレース用メモリ、10……バス制御信号。
The figure is a hardware block diagram when the trace function according to an embodiment of the present invention is operated for program tracing up to parity error detection. 1...CPU, 2...Memory control unit, 3...Memory, 4...Address bus, 5...Data bus,
6... Parity detection signal, 7... Trace control unit, 8... Address trace memory, 9... Data trace memory, 10... Bus control signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 計算機システムにおいて、トレース機能として
トレースしたアドレスやデータを格納するトレー
ス用メモリと、CPUがプログラムを実行する過
程で生じるメモリアクセスを監視してバス上に出
力されるアドレスやデータを前記トレース用メモ
リにコピーするとともに、そのトレース用メモリ
からトレース結果を順次読み出すための制御手段
を具備することを特徴とするCPUのメモリアク
セストレース機能内蔵装置。
In a computer system, there is a trace memory that stores traced addresses and data as a trace function, and a trace memory that monitors memory accesses that occur during the process of a CPU executing a program and outputs addresses and data on a bus to the trace memory. 1. A device with a built-in memory access tracing function for a CPU, characterized in that it comprises a control means for copying and sequentially reading trace results from the tracing memory.
JP10967989U 1989-09-21 1989-09-21 Pending JPH0350253U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10967989U JPH0350253U (en) 1989-09-21 1989-09-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10967989U JPH0350253U (en) 1989-09-21 1989-09-21

Publications (1)

Publication Number Publication Date
JPH0350253U true JPH0350253U (en) 1991-05-16

Family

ID=31658252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10967989U Pending JPH0350253U (en) 1989-09-21 1989-09-21

Country Status (1)

Country Link
JP (1) JPH0350253U (en)

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