JPH03182956A - Buffer memory sharing system - Google Patents

Abstract

PURPOSE:To improve the processing capacity of a system by directly addressing/ accessing a memory on a device-side whose data bus bit length is large from a device whose data bus bit length is small. CONSTITUTION:A control circuit 11 for accessing a bus on a 32-bit-device, an address detection/generation circuit 12, a circuit 13 having a bidirectional conversion function of 32-bit data and 16-bit data and a temporary storage function, a circuit 14 having a function detecting whether access from a 16-bit device-side is of a DMA mode or a program mode and a circuit 15 having a function detecting to which position of data in 32-bit data 16-bit data is equivalent are provided. Thus, DMA transfer can be speeded up and MM52 can directly executes addressing by an address for SMM 58 of SmuP if viewed from SmuP 57, whereby a DMA operation and a program mode operation can be mixed. Thus, processing capacity improves.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides a method for connecting devices with different data bus bit lengths, starting from the device with the smaller data bus bit length (e.g. 1 word: 8 bits or 16 bits, etc.). , the data bus bit length is larger (1 word: 32 bits, etc.);

(Prior Art) FIG. 5 is a block diagram showing a conventional memory read/write circuit between devices having different data bus bit lengths. In the figure, C251 is a 32-bit data bus processor (hereinafter abbreviated as μP), 52 is a main memory for μP51 (hereinafter abbreviated as MM), and one word is composed of 32 bits.53 is a device. -Evening 32 bits → 16
Bit conversion ludge circuit (hereinafter abbreviated as BUFA), 54
is a data 16-bit → 32-bit conversion latch circuit (hereinafter abbreviated as BUFB), 55 is an address control circuit (hereinafter abbreviated as ADDCNT), 56 is various bus control circuits such as read/write (hereinafter abbreviated as C0NT). , 57 is 16
Bit data bus processor (hereinafter abbreviated as SμP),
58 is a main memory (hereinafter abbreviated as SMM) for the SμP 57, and one word consists of 16 bits.

59 is a tie left memory access control circuit (hereinafter referred to as DM).
(abbreviated as AC).

Next, the operation when reading the MM52 from the SμP57 in the conventional circuit will be described.

First, SμP57 always sets the address of MM52 to 5MM5.
It is managed separately from address 8. In the case of SμP57 program mode, ADDCNT5 from SμP57
Write the address of MM52 to 5, then C0NT56.
The C0NT56 loads the 32-bit data from the MM52 into the BUFA53 and latches it. Sμ
P57 receives the latch completion report, divides the necessary data into several times (in this case, once or twice), and
Read from A53. Also, I of S LLP 57
In the IMA mode, the address of MM52 and the address of 5MM58 are preliminarily set in the DMAC 59 from the SμP 57, and the DMAC 59 is activated from C. Then, DMAC59 or C0NT56 is activated, and C0NT56 transfers 32-bit data from MM52 to B.
Make UFA53 3 sales latch. After receiving the latch completion report, the DMAC 59 successively reads data from the BUFA 53 several times and writes data to the corresponding address of the 5MM 58.

Also, write from SμP57 to MM52)-operation and 5
At the time of transfer operation by the DMA mote from MM58 to MM52, a similar processing flow occurs via BLIFB54.

(Problems to be Solved by the Invention) However, the conventional device having the above configuration has the following problems.

1) SμP57 sets the address of MM52 and 5MM58 to 2
This requires heavy management, which reduces the processing power of the SμP57 software.

2) During DMA mode transfer, burst transfer is unavoidable, the bus occupancy rate on the SμP57 side becomes high, and real-time performance in rough 1 to software is degraded.

3) When accessing the MM52 from the SμP57 side, continuous alternating access of read/write operations in 16-bit single bit blockram mode and read/write operations by DMA mote is impossible.

The present invention is intended to solve these problems, and achieves faster and simpler memory access time from a device with a smaller data bit length to a device with a larger data bit length, and system processing. The purpose of this invention is to provide a buffer memory sharing method that can improve performance.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a processor control circuit for a device with a small data bus bit length and a device with a large data bus bit length between devices with different data bus bit lengths. In a system in which two processor control circuits are connected by a bus, and in a buffer memory sharing method in which a device with a small data bus bit length accesses the memory in a device with a large data bus bit length, In between, there is a bus control means for accessing the bus on the device side with a large data bus bit length, an address detection and creation means, and a bidirectional conversion between data of different data bus bit lengths, and temporary processing of each data. a cycle detection means for detecting whether the access is from a device with a small data bus bit length, DMA mode, or block RAM mode; The present invention is characterized by the provision of byte position detection means for detecting whether the data corresponds to the position data.

(Function) By having the above configuration, the present invention enables direct addressing access from a device with a small data bus bit length to the memory of a device with a large data bus bit length, and the access time is faster than that of the conventional method. become,
Furthermore, it is possible to write/write alternately or continuously to memories with different absolute addresses in cPU mode and DMA mode from the device side with a small data bus bit length, and the system processing It improves ability.

(Example) Hereinafter, an example of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing a circuit according to an embodiment of the present invention. In this figure, the same reference numerals as in FIG. 5 indicate the same components. As a different component, 11 is a control circuit (hereinafter referred to as Bt) for accessing the bus on the 32-bit device side.
(abbreviated as lSCNT), 12 is an address detection and creation circuit (hereinafter abbreviated as ADDC/G), and 13 is 32-bit data 0.
A circuit (hereinafter abbreviated as BUFMEM) having a bidirectional conversion function of 16-bit data and a time storage function, 14 is a 16
A circuit (hereinafter referred to as
(abbreviated as MODDET), 15 is 16 bit data or 32
Where in the bit data is the low side 1 of the 32 bits?
A circuit (hereinafter referred to as BYTDET) has a function to detect whether the data corresponds to 6 bits or 16 bits on the body
).

Next, the operation of this embodiment will be explained.

First, the allocation of the memory space is set as shown in FIG. 2 so that the memory space of the SμP 57 or the 5MM 58, which is its own memory, can be accessed by managing the address of the memory space of the MM 52. At the time of initial setting, the X address of MM52 and 5MM58
By recognizing the relative address of y, the rest is SμP57
When accessing MM52, it is sufficient to operate as if accessing 5MM58. When SμP57 outputs address y, ADDC/G12 outputs address y as M.
It detects that it is address X of M52, creates address X from y, and accesses MM52.

Now, under the initiative of SμP57, MM52
It is assumed that the program is being executed while reading/writing the data of MM52 in the program mode while performing DMA transfer of the data of 5MM58 to 5MM58, and writing/writing the data of 5MM58 under itself to -1. . FIG. 4 is a time chart showing the temporal 4 (e transition) of these processes.

SμP57 is at time t. Well, since it is running in program mode and DMA operation is required, SμP5
7 is the address of MM52 (actually y+2α of 5MM58
) and the address of 5MM58 to DMAC59 and start up. Then, at time t1, DMA (:59 operates, and MM52 note & (21!1) via BUSCNT11
ec) (D is taken into BUFMEM13 and 5
■■ data is transferred to MM58. Next, time t3
When the next DMA transfer request is issued at the time of
, by ADDC/G12 and MODDET14■■◎■
It is detected that the data of has already been written to BUFMEM13, and DMAC59 writes it from BUFMEM13.
The data of O is taken in and transferred and written to 5MM58. Next, when the next DMA transfer request is issued at time t5, the DMAC 59 accesses the MM 52, but
BYTDETI5. ADDC/G12 and MODDET
Due to 14, the data of ■[F]■■ is BUFMEM1
It is detected that it is not incorporated into 3. Go to MM52 and access it, import the data of ■[F]◎■ into BUFMEM13 and at the same time import the data of [F] and [F] to 5MM.
It is transferred and written to 58. Also, when a DMA transfer request is issued at time t7, it detects that it has been written to BUFMEM13 in the same way, and transfers °r DMA (:59 is 11UF
Data is fetched from MEM13 and ◎0 data is transferred and written to 5MM58. From now on, in DMA transfer,
Similar actions are repeated. Also, time t2. t4.
Even at t, t8, the SμP57 can read/write the data of the MM52 in the program mode, and at the time of reading, similar to DMA transfer, after taking it into the BUFMEM13, the SμP57 can read/write the data of the MM52.
4 and BYTDETI5, it is possible to directly take in the data at the corresponding bit position into the internal register of the SμP57. When writing, BYTDETI 5 and M
After confirming that 32 bits worth of data has been accumulated by ODDET14, the write operation starts, so MM52
It is possible to reduce erroneous data writing to the MM 52 and shorten the access time to the MM 52.

Note that the DMA write operation is almost the same as the DMA read operation, so the details will be omitted.

0 (Effects of the Invention) As described in detail above, according to the present invention, it is possible to increase the speed of DMA transfer, and when seen from the SμP, the SMM address MM of the SμP directly addresses the DMA transfer. It is possible to mix operation and program mote operation. Therefore, it is expected that the processing capacity on the SμP side will be greatly improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a circuit of an embodiment of the present invention, Fig. 2 is a diagram showing the allocation of memory spaces between the MM and SMM in Fig. 1, and Fig. 3 is a diagram showing the DMA transfer of MM data to the SMM. FIG. 4 is a time chart showing the operation of this embodiment, and FIG. 5 is a block diagram showing a memory read/write path between conventional devices having different data bus bit lengths. 11・ ・ BUSCNT, 12・ ・
・ADDC/G. 13・ ・ BUFMEM, 14◆
・・MODDET. 15. ◆ BYTDET. 51・ 53・ 55・ 57◆ 59・ ・ ・ μP, ◆ ・ BUFA.・ ・ ADDCNT.・ ・ SμP, ・ ・DMAC0 52・ 54・ 56・ 58◆ ・MM.・BUFB.・CONT.・SMM.

Claims (1)

[Scope of Claims] A system in which a processor control circuit of a device with a small data bus bit length and a processor control circuit of a device with a large data bus bit length are connected by a bus between devices with different data bus bit lengths. In a buffer memory sharing method in which a device with a small data bus bit length accesses the memory in a device with a large data bus bit length, the bus of the device with a large data bus bit length is accessed between the buses of both devices. address detection and creation means; means for bidirectional conversion between data of different data bus bit lengths and temporary storage of each data; Access is D
A cycle detecting means for detecting whether the mode is MA mode or program mode, and a byte position detecting means for detecting which position of data of a small data bus bit length corresponds to data of a large data bus bit length are provided. A buffer memory sharing method characterized by: