JPH0357239A - Test circuit pattern for semiconductor - Google Patents

Test circuit pattern for semiconductor

Info

Publication number
JPH0357239A
JPH0357239A JP19348589A JP19348589A JPH0357239A JP H0357239 A JPH0357239 A JP H0357239A JP 19348589 A JP19348589 A JP 19348589A JP 19348589 A JP19348589 A JP 19348589A JP H0357239 A JPH0357239 A JP H0357239A
Authority
JP
Japan
Prior art keywords
time
measuring
mos
constant current
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19348589A
Other languages
Japanese (ja)
Inventor
Tomie Usui
臼井 登美江
Yutaka Saito
豊 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP19348589A priority Critical patent/JPH0357239A/en
Publication of JPH0357239A publication Critical patent/JPH0357239A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To shorten a measuring time by a method wherein a series connection circuit which is formed on a semiconductor wafer and which is composed of constant current circuits and of MOS diodes is constituted so that an electric current can be applied simultaneously to each MOS. CONSTITUTION:Constant current circuits are formed in series with MOS diodes 2 and individual circuit patterns are connected in parallel with a voltage source 3 to constitute a measuring circuit. When a voltage drop is measured at this time, a voltmeter 4 which can be scanned in a time-sharing manner is used. In conventional cases, it took several seconds to several tens of seconds to measure one point; in some cases, several hundred points had to be measured; it took a considerable time for this measurement. By this method, a measuring operation has nothing to do with the number of measuring points; a measuring time is only a longest point time which elapses until a MOS diode in a pattern is broken down; thereby, a whole measuring operation can be finished in this point time.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体ウェハー上に形成される試験回路パタ
ーンに関する. 〔発明の概要1 本発明は,半導体ウェハーの所定箇所に設けられた試験
回路用パターンに定電流回路を内蔵することで,従来数
箇所〜数百箇所の測定を行う際に何十時間ちかかるとい
う問題を解決した.[従来の技術1 従来,半導体ウェハーの所足箇所に設けられた試験回路
パターンは,第2図に示す構成であり,これに電流源を
接続して第4図の試験回路を形成して試験回路パターン
として形成された多数のMOSダイ才一ド2の特性を順
次試験していた.〔発明が解決しようとする課題} しかし、上記構成では,各MOSグイ才一ドを順次測定
するので,数箇所から数百箇所に及ぶ測定を行うには,
場合によっては何十時間らかかるという問題点があった
. 本発明は、上記問題点を解決した改良された試験回路パ
ターンの提供を目的とする. 1課題を解決するための手段〕 本発明が上記目的を達成するために採用した手段は、試
験回路パターンとして,定電流回路とMOSダイオード
との直列接続回路を構成したことにある. [作用I MOSダイオードに定電流回路を直列に設けたことで、
実際の試験測定回路は,第3図に示す構成とすることが
できるので,電圧源を各回路バタ−ンに並列に接続する
ことにより測定回路が構成される. したがって、電圧計Vを時分割することにより多数の測
定箇所を短時間に測定することが可能になる。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test circuit pattern formed on a semiconductor wafer. [Summary of the invention 1] The present invention incorporates a constant current circuit into the test circuit pattern provided at predetermined locations on a semiconductor wafer, thereby reducing the time required to perform measurements at several to hundreds of locations, which would previously take tens of hours. This problem was solved. [Prior art 1] Conventionally, the test circuit pattern provided at the required location on a semiconductor wafer has the configuration shown in Fig. 2, and a current source is connected to this to form the test circuit shown in Fig. 4 for testing. The characteristics of a large number of MOS dies formed as circuit patterns were sequentially tested. [Problem to be solved by the invention] However, in the above configuration, each MOS guide is measured sequentially, so it takes a long time to measure from several to several hundred locations.
The problem was that it could take dozens of hours in some cases. The present invention aims to provide an improved test circuit pattern that solves the above problems. Means for Solving 1 Problem] The means adopted by the present invention to achieve the above object is to configure a series connection circuit of a constant current circuit and a MOS diode as a test circuit pattern. [Action I By providing a constant current circuit in series with the MOS diode,
The actual test and measurement circuit can have the configuration shown in Figure 3, so the measurement circuit is constructed by connecting a voltage source in parallel to each circuit pattern. Therefore, by time-sharing the voltmeter V, it becomes possible to measure a large number of measurement points in a short time.

[実施例] 以下定電流TDDB試験を例にとって実施例について説
明する. 定電流TDDBは、0.01A/cm”  から数十A
 / c rn’までの定電流を印加しMOSダイ才一
ドなどが破壊するまでの時間、ここで破壊するまでの時
間とは電圧がある一定値以下に下がるまでの時間を指す
が、それの測定を例えばウェハー内数箇所〜数百箇所行
う場合に、各パターン中のMOSダイ才一ドにはそれぞ
れ電流回路が接続されているので、ウェハー上の各パタ
ーンに同時に電圧源を接続して第3図に示す測定回路を
構成することができる. このときの電圧降下の制定は時分割走査が可能な電圧計
を使用して行う. したがって、従来l箇所について数秒〜t’l l O
分の測定時間がかかり、場合によっては数百箇所に及ぶ
測定には全体として何十時間もかがることがあった測定
時間が、本発明では測定箇所の数に無関係になるため、
測定時間はパターン中のMOSダイオードが破壊するま
での時間の最ち長くかかったポイント時間のみで全体の
−11定が終了する. [発明の効果] 定tit流回路を試験用バクーンに内蔵したことにより
、各MOSに同時に通電することが可能になったため、
前述した定電流TDDB試験のような測定の大幅な時間
短縮が得られる.
[Example] Examples will be described below using a constant current TDDB test as an example. Constant current TDDB is from 0.01A/cm” to several tens of A
The time it takes for a MOS die to break down when a constant current of up to / crn' is applied. Here, the time to break down refers to the time it takes for the voltage to drop below a certain value. When measuring, for example, several to hundreds of locations on a wafer, a current circuit is connected to each MOS die in each pattern, so a voltage source is connected to each pattern on the wafer at the same time. The measurement circuit shown in Figure 3 can be constructed. The voltage drop at this time is established using a voltmeter capable of time-division scanning. Therefore, conventionally it takes several seconds to t'l l O
The measurement time that used to take several minutes, and in some cases could take tens of hours overall for measurements at hundreds of locations, is now independent of the number of measurement locations.
The measurement time is only the point time that takes the longest time until the MOS diode in the pattern breaks down, and the overall -11 constant is completed. [Effects of the invention] By incorporating a constant tit current circuit into the test vacuum, it became possible to energize each MOS at the same time.
This can significantly shorten the time required for measurements such as the constant current TDDB test described above.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例を示す試験回路パターンを
示す図、第2図は、従来の試験回路パターンを示す図、
第3図は、第1図の試験回路パターンを用いた測定回路
の構成図、第4図は、第2図の試験回路パターンを用い
た試験回路の構成図である。 ・定電流回路 ・MOSダイ才一ド ・電圧源 ・時分割走査する電圧計 ・電流計 ・電圧計 半導体ウェハー内の試験回路パター ン部 ・半導体ウェハー内の試験回路Bター ン部 以上
FIG. 1 is a diagram showing a test circuit pattern showing an embodiment of the present invention, FIG. 2 is a diagram showing a conventional test circuit pattern,
3 is a block diagram of a measuring circuit using the test circuit pattern of FIG. 1, and FIG. 4 is a block diagram of a test circuit using the test circuit pattern of FIG. 2.・Constant current circuit ・MOS die capacitor ・Voltage source ・Voltmeter for time division scanning ・Ammeter ・Voltmeter Test circuit pattern part in semiconductor wafer ・Test circuit B turn part and above in semiconductor wafer

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェハー上に形成され、定電流回路とMOSダイ
オードとの直列接続回路からなる半導体用試験回路パタ
ーン。
A test circuit pattern for semiconductors formed on a semiconductor wafer and consisting of a series connection circuit of a constant current circuit and a MOS diode.
JP19348589A 1989-07-25 1989-07-25 Test circuit pattern for semiconductor Pending JPH0357239A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19348589A JPH0357239A (en) 1989-07-25 1989-07-25 Test circuit pattern for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19348589A JPH0357239A (en) 1989-07-25 1989-07-25 Test circuit pattern for semiconductor

Publications (1)

Publication Number Publication Date
JPH0357239A true JPH0357239A (en) 1991-03-12

Family

ID=16308818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19348589A Pending JPH0357239A (en) 1989-07-25 1989-07-25 Test circuit pattern for semiconductor

Country Status (1)

Country Link
JP (1) JPH0357239A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007150007A (en) * 2005-11-29 2007-06-14 Sumco Corp Semiconductor device evaluation method and semiconductor device manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007150007A (en) * 2005-11-29 2007-06-14 Sumco Corp Semiconductor device evaluation method and semiconductor device manufacturing method

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