JPH0358538A - Synchronism detecting circuit - Google Patents

Abstract

PURPOSE:To improve the accuracy of synchronism establishment by using a synchronism detecting signal counter to count a detected synchronous signal and comparing the counted value with an optional setting value at a synchronism detection number setting register to detect the synchronous signal. CONSTITUTION:Every time a synchronism detection comparator 3 detects synchronous signal, the signal is counted by a synchronism detection counter 4 and the counted value is compared with a value set at a synchronism detection number setting register 6 at a synchronism detection signal comparator 5 and when the counted values of the synchronism detection counter 4 and the value of the synchronism detection number setting register 6 are coincident, a synchronism detection signal (I) 7 is outputted. When the coincidence of synchronism is detected once, the succeeding synchronism detection is attained by the start of operation of a reception data shift register 2 with a reception start signal 8 again after the reset of the reception data shift register 2 and the synchronism detection signal counter 4 by a synchronism detection starting signal 10 or the stop of the reception data shift register 2 by the reception start signal 8. Thus, the synchronism establishment accuracy is improved.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a synchronization detection circuit, and in particular, in a character synchronization establishment method for serial data transmission, HDLC, S of a synchronization establishment signal generation circuit for a received character for synchronization detection is used.
This invention relates to a DLC flag synchronization establishment circuit.

[Conventional technology]

Conventionally, HDLC (high level data
link control procedures), S
Flag synchronization using the DLC protocol establishes synchronization if there is one normal flag pattern at the start of the reception operation, and after that, characters other than the flag pattern can be received. In addition, once the synchronization of the flag pattern has been established after the start of the reception operation, in order to establish synchronization again, it is necessary to stop the reception operation or use a control signal to establish synchronization using the flag pattern. It became. FIG. 2 is a block diagram showing a conventional synchronization detection circuit.

In Figure 2, the conventional synchronization detection circuit
It includes a shift register 2 and a comparator 3 for detecting a synchronizing signal. The synchronization detection signal (■) 9 outputs a synchronization coincidence signal detected by the synchronization signal detection comparator 3 from the serial data received by the reception data shift register 2. This synchronization match signal is used as a synchronization detection signal (I ) 7 and synchronization detection signal (■) 9 are not output.

The synchronization detection start signal 10 indicates that the serial data received by the reception data shift register 2 which started receiving operation in response to the reception start signal 8 is synchronized again from the serial data after the synchronization signal detection comparator 3 detects the synchronization signal. This is a signal terminal for detecting a signal. Conventionally, when the reception data shift register 2 starts operating in response to the reception start signal 8, the reception of serial data from the reception data input terminal 1 is started. The serial data received by the reception data shift register 2 first starts detecting a synchronization signal. The reception data shift register 2 converts serial data from serial to parallel data according to a determined bit pattern.

Here, a synchronization signal is detected from the received data converted from serial to parallel by a synchronization signal detection comparator 3. When a synchronization signal is detected in the serial data received from receive data shift register 2, a synchronization detection signal (■)
9 is output, and the synchronization detection ends. The means for detecting a synchronization signal while the reception data shift register 2 is in operation using the reception start signal 8 detects the synchronization signal using the synchronization detection start signal lO.

[Problem to be solved by the invention]

The establishment of synchronization using flag patterns in the conventional HDLC and SDLC described above was performed using only one flag pattern, and once synchronization was established, data reception status was established. There is a drawback that incorrect data etc. may be received.

Also. In order to synchronize the flags after starting the reception operation,
There is also the drawback that control must be performed using a control signal for establishing synchronization.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization detection circuit which solves the above-mentioned drawbacks, eliminates the risk of receiving invalid data, and allows flag synchronization to be easily achieved.

[Means to solve the problem]

The configuration of the synchronization detection circuit of the present invention includes a counter that counts flag detection signals when receiving a flag pattern, a setting register that sets the detection count number of the counter, a counter value of the counter, and a set value of the register. and a comparator for comparing the.

〔Example〕

It is a block diagram.

In FIG. 1, the synchronization detection circuit of this embodiment includes a reception data shift register 2, a synchronization signal detection comparator 3,
It includes a synchronization detection signal counter 4, a synchronization detection number setting register 6, and a synchronization detection signal comparator 5. Reception data input terminal 1 is an input terminal for serial data from a data transmission line. The reception data shift register 2 receives serial data input from the reception data input terminal 1, performs reception operation based on the clock, and
It has a function of converting serial data to parallel data by receiving operation. The synchronization signal detection comparator 3 has a function of detecting data intended for synchronization from among the received data converted from serial data to parallel data by the received data shift register 2.

The synchronization detection signal counter 4 includes a synchronization signal detection comparator 3
It has a function to count the number of synchronization signals detected. The synchronization detection signal comparator 5 has a function of comparing the synchronization detection signal counter 4 and the number of detections set by the synchronization detection frequency setting register 6, and outputting the synchronization detection signal 7 when the two values match. have

The synchronization detection number setting register 6 is a register for setting the number of synchronization detections, and the value of this register determines the number of synchronization detections. Further, the setting value of the synchronization detection number setting register 6 has a function that allows setting an arbitrary value. The synchronization detection signal (I) 7 is generated when the number of times the synchronization signal is detected by the synchronization detection signal counter 4 and the setting value of the synchronization detection number setting register 6 become the same value in the synchronization detection signal comparator 5. , outputs a match signal.

The reception start signal 8 is a signal for starting/stopping the reception of serial data from the reception data input terminal 1 to the reception data shift register 2. Due to the reception start signal 8,
The synchronization signal detection by the synchronization detection comparator 3 from the reception operation of the reception data shift register 2 is the same as the conventional one shown in FIG.

In this embodiment, a synchronization detection signal counter 4 counts the synchronization coincidence signal detected by the synchronization signal detection comparator 3. The synchronization detection signal counter 4 counts each time a synchronization signal is detected by the synchronization detection comparator 3 while the synchronization signal is continuously input into the serial data received by the reception data shift register 2.

The count by the synchronization detection power counter 4 is determined by comparing the value set by the synchronization detection number setting register 6 with the synchronization detection signal comparator 5, and then comparing the count value of the synchronization detection power counter 4 with the value of the synchronization detection number setting register 6. When they match, a synchronization detection signal (I) 7 is output. Here, if the number of synchronization signals in the received serial data in the reception data shift register 2 does not match the number set in the synchronization detection count setting register 6, the number of synchronization signals is changed until the number of synchronization signals reaches the set number. Detection is performed.

Once a synchronization match is output from the synchronization detection signal comparator 5 as the synchronization detection signal (l) 7, subsequent synchronization detection is performed by the reception data shift register 2 and the synchronization detection signal counter according to the synchronization detection start signal 10. 4 or after the reception data shift register 2 is stopped by the reception start signal 8, this becomes possible by starting the operation of the reception data shift register 2 again by the reception start signal 8. In contrast to the conventional HDLC and SDLC reception flag synchronization establishment circuits described above, this embodiment counts the number of times synchronization has been established based on the flag pattern, and establishes synchronization based on the count value and the setting value of the counter register. bring about

〔Effect of the invention〕

As explained above, the present invention detects a synchronization signal detected by a synchronization signal detection comparator as a synchronization detection signal power. By counting using a counter and detecting a synchronization signal by comparing the count value with the arbitrary setting value in the synchronization detection count setting register, the number of synchronization signals detected after the reception operation starts increases and it becomes easier to establish synchronization. In addition to improving accuracy, this has the effect of masking the reception operation caused by the conversion of the synchronization signal into invalid data due to transmission line noise or the like immediately after the start of the reception operation. Further, the present invention has the effect that the number of synchronization detections can be set arbitrarily for each device by providing a register for setting the number of synchronization detections.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a synchronization detection circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional synchronization detection circuit. 1...Reception data input terminal, 2...Reception data shift register, 3...Comparator for synchronization signal detection, 4...Synchronization detection signal counter 5
... Synchronization detection signal comparator, 6 ... Synchronization detection number setting register, 7 ... Synchronization detection signal (
I), 8... Reception start signal, 9... Synchronization detection signal (II), 10... Synchronization detection start signal.

Claims (1)

[Claims] A counter that counts flag detection signals when a flag pattern is received, a setting register that sets a detection count number of the counter, and a comparator that compares the counter value of the counter and the set value of the register. A synchronization detection circuit characterized by: