JPH0487432A - Synchronization protecting circuit - Google Patents

Abstract

PURPOSE:To prevent a fact that a stable synchronizing signal comes not to be obtained at all in the case the circuit state is no good, etc., by constituting the circuit so that it is reset by a reference synchronizing signal outputted from a first synchronization counter at all times, when the synchronization protection is executed by a first synchronization counter, and a second synchronization counter outputs continuously the reference synchronizing signal in the original measuring period, when the synchronization protection comes not to be executed. CONSTITUTION:When the synchronization protection is executed, whenever a reference synchronizing signal is outputted, a second synchronization counter 10 is reset and an output of an output reference synchronizing signal is started newly. As a result, an output of a second synchronization counter is synchronized with an output of a first synchronization counter 9. At the time of becoming step-out, a flip-flop 11 is reset and a second synchronization counter 10 comes not to be reset, and from the timing before step-out of the synchronization protection, the output of the output reference synchronizing signal is started, based on an original period.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a synchronization protection circuit suitable for use as a synchronization protection circuit on the receiving side in synchronous data transmission, and in particular, to a synchronization protection circuit suitable for use as a synchronization protection circuit on the receiving side in synchronous data transmission. In addition, the present invention relates to a synchronization protection circuit that is effective when transmitting sub-synchronization of 1-bit data in a system that requires sub-synchronization.

[Prior Art] FIG. 3 shows a block diagram of a conventional synchronization protection circuit. This synchronization protection circuit uses a main synchronization signal having a period of Ims as a reference, and transmits a sub-synchronization signal having a period of 9ms using one bit of frame data consisting of nine pits.

In the synchronization protection circuit shown in the figure, the synchronization counter 8 flywheels at a cycle of 9 ms, and the reference synchronization signal output from the synchronization counter 8 and the synchronization detection signal input from the outside match the coincidence detector. 1 and is input to the discrepancy detector 2. When the mismatch detector 2 detects that the reference synchronization signal and the synchronization detection signal do not match, the mismatch counter 4 counts up, and when the mismatch is detected four times, the flip-flop 5 enters the seven-node state. .

When FRI, BUFLO, and BUF5 are set, the synchronization detection signal passes through the AND gate 7 and is input to the reset terminal of the synchronization counter 8 as a pseudo synchronization detection signal. Therefore, the synchronization counter 8 is reset at the input timing of the pseudo synchronization detection signal and starts a new flywheel.

However, if the coincidence detector l determines that the reference synchronization signal and the synchronization detection signal match, the coincidence counter 3 counts up, and the coincidence counter 2 counts up before the mismatch counter 4.
Once counted, the discrepancy counter 4 is reset. Therefore, when the synchronization detection signal and the reference synchronization signal are in good agreement, the synchronization counter 8 is not reset and maintains the synchronization protection tube. Therefore, even if the synchronization is lost, the synchronization signal is maintained unless the mismatch state is detected four times and the pseudo synchronization detection signal is generated.

[Problems to be solved] By the way, since the synchronization signal used here is synchronously transmitted using 1-bit data, there is a higher possibility that mismatches will occur than in synchronization signals that are transmitted in the form of a synchronization pattern. The probability that a synchronization detection signal will be generated is also high.

FIG. 4 shows an example of the operation timing of a conventional synchronization protection circuit.

As shown in the figure, in line conditions where synchronization is not protected, the synchronization detection signal by l-bit transmission almost always causes an error, and the synchronization counter 8 generates a false signal every four times when the mismatch counter 4 counts. Reset by synchronization detection signal.

In the conventional synchronization protection circuit, when synchronization protection is lost due to line deterioration, the synchronization counter 8 is reset at any time by a pseudo synchronization detection signal. Therefore, if the line condition is poor, stable synchronization signals and other timing signals cannot be obtained.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a synchronization protection circuit that can prevent a stable synchronization signal from being completely unavailable when the line condition is poor. do.

[Means for Solving the Problems] In order to achieve the above object, the invention according to the first claim provides a first synchronization counter that flywheels at the same period as a predetermined synchronization detection signal and outputs a first reference synchronization signal. a synchronization protection determining means for determining whether or not to maintain the synchronization protection state by detecting a match or mismatch between the first reference synchronization signal and the synchronization detection signal; a first synchronization control means for controlling the first synchronization counter to synchronize with the synchronization detection signal when it is determined that the synchronization counter should not be maintained; and a second synchronization counter having the same period as the first synchronization counter. The second one outputs the reference synchronization signal.
a synchronization counter, and a second synchronization counter that synchronizes the second synchronization counter with the first synchronization counter when it is determined by the synchronization protection determining means to maintain synchronization protection.
The configuration includes a synchronization control means.

Further, the invention according to the second claim is the synchronization protection circuit according to the first claim, in which the second synchronization counter is configured to output the second reference synchronization signal from the time when a predetermined control signal is input. The second synchronization control means is configured to start the first reference synchronization signal as the control signal when the synchronization protection determining means determines that the synchronization protection is to be maintained. It is configured to include a control section that causes input to the synchronous counter.

[Operation] In the invention according to the first claim configured as described above, the first synchronization counter flywheels at the same period as the predetermined synchronization detection signal and outputs the first reference synchronization signal,
The synchronization protection determining means detects the match or mismatch state between the first reference synchronization signal and the synchronization detection signal and determines whether or not to maintain the synchronization protection state. The first synchronization counter is controlled to be synchronized with the synchronization detection signal when the protection determining means determines that synchronization protection should not be maintained. Further, the second synchronization counter outputs a second reference synchronization signal having the same cycle as the first synchronization counter, and the second synchronization control means is determined to maintain synchronization protection by the synchronization protection determination means. In this case, the second synchronization counter is synchronized with the first synchronization counter.

That is, the first synchronization counter independently performs synchronization protection of the synchronization detection signal, and when the first synchronization counter performs synchronization protection, the second synchronization counter performs synchronization protection of the synchronization detection signal. It is controlled to be synchronized with. Therefore, when synchronization protection is performed by the first synchronization counter, the second synchronization counter is also synchronized with the first synchronization counter, so a stable reference synchronization signal is obtained, and the first synchronization counter When synchronization protection is not performed, the second synchronization counter continues to output the reference synchronization signal independently, so a stable reference synchronization signal is output in any case.

Further, in the invention according to the second claim configured as described above, the second synchronization counter starts outputting the second reference synchronization signal from the time when a predetermined control signal is input,
The control unit in the second synchronization control means causes the first reference synchronization signal to be input to the second synchronization counter as the control signal when it is determined by the synchronization protection determining means to maintain synchronization protection. .

That is, whenever synchronization protection is performed by the first synchronization counter, the second synchronization counter is reset by the reference synchronization signal output from the first synchronization counter and starts outputting the second reference synchronization signal. However, when synchronization protection is no longer performed by the second synchronization counter, the second synchronization counter independently continues and outputs the second reference synchronization signal at a predetermined period.

[Example] Hereinafter, the present invention will be described in detail based on the drawings. Note that common reference numerals are given to parts that are common or correspond to the conventional example.

FIG. 1 shows a block diagram of a synchronization protection circuit according to an embodiment of the present invention.

In the figure, the first synchronization counter 9 flywheels at a period of 9ms, and the first synchronization counter 9 sends the reference synchronization signal to the coincidence detector and mismatch detector 2 every 1ms from the reset timing. It is output to. If the input timings of the synchronization detection signal and the reference synchronization signal match, the coincidence detector 1 outputs a coincidence detection signal to the coincidence counter 3, and when the coincidence detection signal is input, the coincidence counter 3 counts up and outputs the coincidence detection signal. When the count value reaches 2, a coincidence count signal is output. Further, the mismatch detector 2 outputs a mismatch detection signal to the mismatch counter 4 when the input timings of the synchronization detection signal and the reference synchronization signal do not match, and the mismatch counter 4 counts up and down when the mismatch detection signal is input. When the count value reaches 4 by turning the knob, a mismatch count signal is output.

The flip-flop 5 is set by the mismatch count signal output from the mismatch counter 4, and the AND circuit 7 outputs the synchronization detection signal as a pseudo synchronization detection signal to the first synchronization counter 9 when the flip-flop 5 is in the seven-node state.
input to the reset terminal.

The output of the AND circuit 7 is also input to the OR circuit 6 together with the coincidence count signal output from the coincidence counter 3.
The output of the OR circuit 6 is input to the reset terminals of the match counter 3, the mismatch counter 4, and the flip-flop 5.

Furthermore, the coincidence count signal output from the coincidence counter 3 is input to the set terminal of the flip-flop 11, and the mismatch count signal output from the coincidence counter 4 is input to the reset terminal of the flip-flop 11. The output of the flip-flop 11 is input to one terminal of an AND gate 12, and the reference synchronization signal output from the first synchronization counter 9 is input to the other terminal of the AND gate 12. The output of the AND gate 12 is input to the reset terminal of the second synchronous counter 10, and the flip-flop 11 and the AND gate 12 constitute a control circuit for the second synchronous counter.

Note that the second synchronization counter 10 outputs an output reference synchronization signal having the same cycle as the first synchronization counter 9 from the reset timing.

In this configuration, when the synchronization between the initial synchronization detection W signal and the reference synchronization signal does not match, the mismatch detector 2 outputs a mismatch detection signal every time a synchronization detection signal is input, and the mismatch counter 4 detects the same synchronization. Count the number of signal inputs. When the same number of times reaches 4, the mismatch counter 4 outputs a control signal to set the flip-flop 5. Therefore, when the synchronization detection signal is input after the same state is reached, the same synchronization is performed via the AND circuit 7. The detection signal is input to the reset terminal of the first synchronous counter 9, and the first synchronous counter 9 is reset. Since the first synchronization counter 9 starts outputting the reference synchronization signal at the reset timing, the synchronization detection signal input to the reset terminal acts as a pseudo synchronization detection signal, and from then on, the first synchronization counter 9 starts outputting the reference synchronization signal. The output reference synchronization signal is synchronized with the synchronization detection signal.

If the synchronization detection signal and the reference synchronization signal match,
The coincidence detector l outputs a coincidence detection signal every 1 ms to count up the coincidence counter 3.
outputs a coincidence count signal every time it counts the same coincidence detection signal twice.

The coincidence count signal is input to the OR circuit 6, and when the OR circuit 6 receives the signal, it resets the coincidence counter 3 and the disagreement counter 4, and also puts the flip-flop 5 into a reset state.

As a result, as long as the synchronization detection signal and the reference synchronization signal match, the first synchronization counter 9 continues to flywheel without being reset, and the synchronization protection process continues.

On the other hand, if an error occurs in the synchronization detection signal due to a data error occurring on the line, the mismatch detector 2 detects a mismatch between the synchronization detection signal and the reference synchronization signal, and the mismatch counter 4 starts counting up based on the mismatch detection signal. be done. Then, when the mismatch counter 4 counts up to four times, the flip-flop 5 is set in the same manner as at the beginning of startup, and the first synchronization counter 9 is reset by the next input synchronization detection signal.

Normally, the synchronization detection signal and the reference synchronization signal sometimes match and sometimes do not match, and when the match counter 3 counts up to two times, the match count signal causes a match with the flip-flop and block 5 via the OR gate 6. The counter 3 and the mismatch counter 4 are reset to protect the synchronization. However, if the mismatch counter 4 counts four times first, the synchronization protection is lost, and the synchronization detection signal detected after the counter resets the first synchronization counter 9. It will be reset and look for a new sync position.

However, in this embodiment, the reference synchronization signal output from the first synchronization counter 9 is input to one terminal of the AND gate 12, and the output of the AND gate 12 is connected to the reset terminal of the second synchronization counter 10. has been done.

On the other hand, the output of the flip-flop 11 is connected to the other terminal of the AND gate 12, and the flip-flop 11 is set by the coincidence count signal and reset by the mismatch count signal.

Therefore, when the synchronization protection is performed, the coincidence count signal is input to the set terminal of the flip-flop 11, and the output of the flip-flop 11 causes the AND
The reference synchronization signal output from the first synchronization counter 9 can pass through the gate 11. Therefore, every time the reference synchronization signal is output, the second synchronization counter 10 is reset and starts outputting a new output reference synchronization signal. Since the second synchronization counter 10 starts outputting the output reference synchronization signal at the reset timing, the output of the second synchronization counter 10 is synchronized with the output of the first synchronization counter 9. This synchronization protection circuit outputs a reference synchronization signal whose synchronization is protected.

On the other hand, if the synchronization is lost, the mismatch count signal is input to the reset terminal of the flip-flop 11, so the flip-flop 11 is reset. Therefore, the reference synchronization signal output from the first synchronization counter 9 is A
It cannot pass through the ND gate 12, and the second synchronization counter 10 is no longer reset by the same reference synchronization signal.

Therefore, the second synchronization counter 10 starts outputting the reference synchronization signal for output based on the original cycle of the second synchronization counter 1O from the timing before the synchronization protection is removed.

Solution 2 Figure 2 shows an example of the operation timing of the synchronization protection circuit in this embodiment.

As shown in the figure, even if the synchronization protection is lost, the synchronization signal can be stably obtained from the second synchronization counter 10.

When the synchronization protection is lost, the first synchronization counter 9 searches for a synchronization position even though it is disturbed by the mismatch count signal, and when synchronization is established and a match count signal can be obtained from the coincidence counter 3, the first synchronization counter 9 searches for the synchronization position again. The second synchronization counter IO begins to be reset by the reference synchronization signal output by the synchronization counter 9.

[Effects of the Invention] As explained above, the present invention allows a stable synchronization signal to be obtained by the second synchronization counter even when there are a large number of data errors due to deterioration of the line, and a stable synchronization signal can be obtained based on the same synchronization signal. A synchronization protection circuit capable of obtaining other timing signals can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a synchronization protection circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation timing of the synchronization protection circuit shown in FIG. 1, and FIG. 3 is a block diagram of a conventional synchronization protection circuit. FIG. 4 is a timing chart showing an example of the operation timing of the synchronization protection circuit shown in FIG. l... Match detector, 2... Mismatch detector, 3...
Coincidence counter, 4... Mismatch counter, 5... Flip-flop, 6... OR circuit, 7... AND circuit, 9... First synchronous counter, 10... Second synchronous counter , ll...furi nobufuro nobu, l 2
...AND gate.

Claims (2)

[Claims] (1) A first synchronization counter that flywheels at the same period as a predetermined synchronization detection signal and outputs a first reference synchronization signal, and a match or mismatch state between the first reference synchronization signal and the synchronization detection signal. a synchronization protection determining means for determining whether or not to maintain the synchronization protection state by detecting the synchronization protection state; and when the synchronization protection determination means determines that synchronization protection should not be maintained, the first synchronization counter sets Synchronization is performed by a first synchronization control means that performs control to synchronize with the detection signal, a second synchronization counter that outputs a second reference synchronization signal having the same cycle as the first synchronization counter, and the synchronization protection determination means. A synchronization protection circuit comprising: second synchronization control means for synchronizing the second synchronization counter with the first synchronization counter when it is determined that protection is to be maintained. (2) In the synchronization protection circuit according to the first claim, the second synchronization counter is configured to start outputting the second reference synchronization signal upon input of a predetermined control signal; The second synchronization control means has a control section that causes the first reference synchronization signal to be input to the second synchronization counter as the control signal when it is determined by the synchronization protection determining means to maintain synchronization protection. A synchronization protection circuit characterized by being configured as follows.