JPH0360067A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] A method of isolating elements in an integrated circuit semiconductor device, in which isolation regions between elements in an integrated circuit semiconductor device are formed by self-aligning with electrodes of semiconductor elements. The present invention aims to provide a method for manufacturing an integrated circuit semiconductor device in which a semiconductor element having one pair of current electrodes and a control electrode is integrated on a semiconductor substrate. The bottom of the tank is formed to include a step of covering an intermediate region with a mask, and a step of implanting inactivation ions into the semiconductor substrate through the mask and electrode to form an element isolation region around the semiconductor element.

[Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for isolating elements of an integrated circuit semiconductor device.

In recent years, with the increase in the scale of semiconductor integrated circuits, semiconductor elements have been increasingly miniaturized. To achieve this, it is desired not only to miniaturize elements or electrodes, but also to miniaturize element regions or active regions forming the elements, and therefore it is desirable to form elements accurately within the microscopic active regions.

[Prior Art] FIGS. 2(A) and 2(B) show a method of manufacturing a semiconductor device according to a conventional technique.

First, as shown in FIG. 2(A), a mask 52 covering the active region 55 is formed on the surface of the semiconductor substrate 5i, and the inactivated ions 53, for example, oxygen ions, are passed through the mask 52. Ions are implanted into the entire surface of the semiconductor substrate 51 to form isolation regions 54.

That is, active region 55 is formed in a region surrounded by isolation region 54 .

Thereafter, a device structure is formed in the active region 55 thus defined. For example, a pair of source and drain electrodes 56 and 57, which are current electrodes, and a gate electrode 58, which is a control electrode for controlling current, are formed on the surface of the element region 55 of the semiconductor substrate 1.

Here, as the mask 52, resist or metal can be used. In the case of a resist, for example, a resist AZ available from Cypres is formed to a thickness of about 1.5 μm and patterned by exposure. In the case of a metal mask, a metal layer is first formed, a resist layer is formed thereon, the resist layer is exposed to Jm and developed, and a pattern of the resist layer is first formed. The pattern of this resist layer is transferred to a metal layer to form a metal layer pattern. Inactivation ion 5
As 3, when the semiconductor is GaAs, oxygen ions or the like can be used. In addition, if it can convert a semiconductor into a high resistance state, it can be used as a passivating ion.

According to current photolithography technology, it is difficult to perfectly match the boundaries between the source/drain electrodes 56 and 57 and the isolation region 54, and a margin of about 0.5 μm is usually desired4.Therefore, a total of 1 μm on both sides is required. degree of extra width is required.

[Problems to be Solved by the Invention] According to the conventional technology described above, since a semiconductor element is formed in the active region 55, the size of the active region 55 is determined based on the size necessary for the semiconductor element, taking into account the accuracy of mask alignment. It had to be larger than the actual area. In other words, the area utilization rate of the conductor substrate is hindered by the accuracy of mask alignment.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which isolation regions between elements in an integrated circuit semiconductor device can be formed in self-alignment with electrodes of semiconductor elements.

[Means for Solving the Problems J] FIGS. 1A, 1B and 1B are explanatory diagrams of the principle of the present invention.

First, as shown in FIG. 1A, electrodes of a semiconductor element are formed on a semiconductor substrate 1. For example, a pair of current electrodes 2.3 and a control electrode 4 therebetween are formed.

After forming the electrodes, the area between the electrodes is covered with a mask 5, as shown in FIG.
In the case shown in Figure 6, in which inactivated ions 0 are implanted using a mask, the ends of the pair of current poles 2.3 become the effective ends of the mask, and the current f! For example, the semiconductor element is a field effect transistor, t[i2.3 is the source/drain electrode 4, and pole 4 is the gate electrode. . The deactivating ions 6 are, for example, oxygen ions. The mask 5 can be made of a resist layer, a metal layer, etc., for example.

[Operation] After forming the electrodes, the inter-electrode region is covered with a mask 5 and inert ions 6 are implanted, so that the ends of the electrodes (in the illustrated case, the source/drain electrodes 2 and 3) are effectively masked. Since the mask 5 does not require precision mask alignment, the separation region 7 is formed in a form that is self-aligned with the electrode. Electric [! Since the intervening region is covered with the mask 5, it is not affected by the passivating ions 6, and therefore the element region can be formed with the minimum necessary area.

[Example] Figures 3A to 3D show HEMTs according to examples of the present invention.
A method of manufacturing an integrated circuit semiconductor device is shown.

Although one HEMT is shown in the figure, it is assumed that a large number of HEMTs are created on the substrate. The HEMT semiconductor substrate 1 usually has a plurality of layers.

For example, a GaAs buff layer on a GaAS substrate, a GaAs
As electron transport layer, n-type AlGaAs electron supply layer, GaA
An s# thick layer and the like are formed. In addition, AlGaAs is used for adjustment of enhancement mode and depletion mode.
In Figure 0, in which a stopper layer, a GaAs cap layer, etc. are used, only a base crystal layer 11, an electron transit layer 12, and an electron supply layer 13 are shown. , a gate pole 4 is formed. The travel of the two-dimensional electron gas 14 formed on the surface of the electron travel layer 12 is controlled by the gate voltage of the gate electrode 4 .

FIG. 3(B) is a plan view showing the thousand-sided ellipse of the electrode. As shown in FIG.
Drain electrodes 3 are arranged in parallel along the X direction and face each other. A gate electrode @4 is placed between the source electrode 2 and the drain electrode 3.

One end of gate t tri 4 is bonding pad 4a
It is continuous.

For example, the distance between the source electrode 2 and the train Hi3 is about 2 μm, and the width of the gate electrode 1Ff14 is about 0°5 μm.
It is. The source electrode 2 and the drain electrode 3 are formed of, for example, a lower layer of Auae with a thickness of about 1000 people and an upper layer of ^U with a thickness of about 4000 people. Further, the gate electrode 4 is composed of, for example, a lower layer of Ti with a thickness of about 1,000 thick, a middle layer of PT with a thickness of about 1,000 thick, and an upper layer of Au with a thickness of about 3,000 thick.

As shown in FIG. 3(C), cover the inter-electrode region with a mask 5, for example, with a layer of resist AZ having a thickness of about 1.5 μm or more, between the source electrode [i2 and the gate electrode 4 and between the gate electrode 4 and the gate electrode]. A mask 5 is formed to cover the space between the drain electrode 4 and the drain electrode 3.

If the resist has insufficient ion-stopping ability,
After forming an insulating film such as a glabellar insulating film or a surface protection film such as SiO, SiON, etc., a metal layer is formed, a resist layer is formed on it, and the resist layer is patterned. A metal layer mask 5 having a predetermined shape is formed by transferring the metal layer to a layer.

Next, as shown in FIG. 3(D), inactivation ions 6 such as oxygen ions are implanted into the entire surface. The element area is masked with mask 5.
and t@2.3.4, the passivation ions are blocked and the 9-electrode [i2.3.4] does not reach the semiconductor layer.
Outside the edge of the electron supply layer 1, the inactivated ions
3 and penetrates to a level below the electron transport layer 12 to form a separate head 7. For example, as an inactivated ion, the acceleration energy of oxygen ion 6 is 100 to 20
The 0 keV-implantation dose is on the order of 1 x 10 "'cry-".

Note that in the above embodiment, HEM is used as the semiconductor element.
We have explained the case where T is used, but in the same way, MESFET
, field effect semiconductor devices (FET) such as S I 5FET
You can also use Moreover, not only FETs but also semiconductor elements such as bipolar transistors, etc., can have ! [! A similar manufacturing method can be used if the element defines the outline of the element region.

Although the case where oxygen is used as the passivating impurity has been described, this method takes advantage of the fact that when GaAs is doped with oxygen, it becomes semi-insulating. Similarly, when InP is used as a semiconductor, it may be doped with Fe, or any other material may be used as long as it can inactivate (increase resistance) the semiconductor forming the element region.

4(A) and 4(B) show a method for manufacturing a semiconductor device according to another embodiment of the present invention, FIG. 4(A) is a plan view, and FIG.
Figure (E) is a cross-sectional view.

A source electrode 22,
The gate electrode 24 and the drain electrode 23 are formed concentrically. The source electrode [22 and the drain electrode 23 are connected to the semiconductor substrate 1
The gate electrode 24 forms an ohmic contact with the surface of the semiconductor substrate 1, and the gate electrode 24 forms a Schottky contact with the surface of the semiconductor substrate 1. Note that a plurality of semiconductor elements having a similar configuration are arranged.

A mask 25 is placed over these electrodes to cover the inter-electrode area.
form. As is clear from FIG. 4(B), mask 2
5 is necessary to cover the region between the source electrode 22 and the gate electrode 24 and between the gate electrode 24 and the drain electrode 23, and the source electrode f! 22. After forming such a mask 25, which may also cover the gate electrode 24, inactivation ions such as oxygen ions are implanted into the entire surface of the semiconductor substrate 1.

In the case of this embodiment, the drain voltage f! 25 defines the outer contour of the semiconductor element, and the boundary between the element region and the isolation region is defined only by the outer edge of the train electrode 23. In the electrode pattern of FIG. 3(B), it was necessary to take into account the accuracy of mask alignment in the y direction, but this is not necessary in this embodiment.

Although the present invention has been described above with reference to examples, it will be obvious to those skilled in the art that the present invention is not limited to these examples, and that, for example, various changes, improvements, combinations, etc. can be made.

[Effects of the Invention] As described above, according to the present invention, an element isolation region can be formed in a self-aligned manner at the t-pole of a semiconductor element itself in an integrated circuit semiconductor device.

It becomes easier to improve the degree of integration of integrated circuits.

[Brief Description of the Drawings] Figures 1(A) and 1(B) are diagrams explaining the principle of the present invention, and Figure 1(A) is a cross-sectional view showing the process of forming a quadrupolar acid. B) is a cross-sectional view showing the ion implantation process; FIGS. 2A and 2B are views showing the conventional technique; FIG. 2A is a cross-sectional view showing the active region definition process; Figure 2 (B) is a cross-sectional view showing the process of manufacturing a semiconductor element, and Figures 3 (A) to (D) are HEMTs according to embodiments of the present invention.
-The LSI manufacturing method is shown, FIG. 3(A) is a cross-sectional view showing the process of electrode creation, and FIG. 3(B) is! FIG. 3(C) is a plan view showing the planar structure of the pole; FIG. 3(C) is a cross-sectional view showing the process of mask formation; FIG. 3(D> is a cross-sectional view showing the step of inactivating ion implantation); , (B) show a method of manufacturing a semiconductor device according to another embodiment of the present invention, in which FIG. 4(A) is a plan view and FIG. 4(B) is a cross-sectional view. 3 1 2 3 4 2 Substrate Current Electrode Control Electrode Mask Deactivation Ion Separation Region Base Crystal Layer Electron Transport Layer Electron Supply Layer Two-dimensional Electron Gas Source Electrode 3 4 5 Drain Electrode Gate Electrode Mask (A) Electrode Formation (B) Ion Implantation (A) Active region definition (B) Semiconductor element fabrication (A) Electrode fabrication (B) Electrode planar structure HEMT LSI manufacturing method according to an embodiment of the present invention Figure 3 (Part 1) (C) Mask formation ( D) Implantation of inactivation ions FIG. 3 (Part 2) of HEMT LSI manufacturing method according to an embodiment of the present invention

Claims (2)

[Claims] (1) A method for manufacturing an integrated circuit semiconductor device in which a semiconductor element having a pair of current electrodes (2, 3) and a control electrode (4) is integrated on a semiconductor substrate (1), the method comprising: A step of covering the inter-electrode region with a mask (5), and implanting passivating ions (6) into the semiconductor substrate (1) through the mask (5) and the electrodes (2, 3, 4) to form the semiconductor element. A method for manufacturing a semiconductor device, comprising the step of forming an element isolation region (7) around the periphery. (2) The step of covering with a mask is to form a metal layer on the surface of the semiconductor substrate on which electrodes are formed via an insulating film, form a resist layer on top of the metal layer, pattern the resist layer, and form a resist layer pattern. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising transferring to a metal layer.