JPH0360512A - Digital equalizer - Google Patents

Abstract

PURPOSE:To shorten time for transfer from a first memory to a digital signal processing circuit by transferring the contents of the first memory to a second memory by a first transferring means and transferring the contents of the second memory to the digital signal processing circuit by a second transferring means. CONSTITUTION:The first transferring means 61 reads out the coefficient, which is stored in a ROM 41, corresponding to digital signal processing circuits DSP 51-5m and adds necessary arithmetic processing for shaping a form so that data can be transferred to the respective DSPs as they are. Afterwards, the contents are stored in RAMs 71-7m. The contents stored in the RAMs 71-7m are successively transferred to the correspondent DSPs 51-5m by the second transferring means 8. As the first transferring means 61, a microcomputer, etc., is used and as the second transferring means 8, however, a simple and high-speed means such as a DMA controller, etc., is used. Accordingly, the contents can be transferred from the RAMs 71-7m to the DSPs 51-5m in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital equalizer, such as a graphic equalizer or a parametric equalizer, which equalizes a digital audio signal to a predetermined frequency characteristic.

[Conventional technology]

Conventionally, when equalizing an audio signal to a desired frequency characteristic, analog processing has been performed. However, recently, with the spread of digital audio equipment, the number of devices that perform digital processing has increased.

When digitally equalizing an audio signal,
Because there is less deterioration in sound quality, linear phase acyclic (FIR) digital filters are used instead of recursive (IIR) digital filters.
) Digital filters are increasingly being used.

FIG. 3 is a block diagram showing the configuration of an example of an acyclic (FIR) digital filter.

In the same figure, 11 to in is 1 when the input signal X(n) is
Delay circuits that delay by a sampling clock and sequentially output to subsequent stages; 21 to 2n are multipliers that multiply input signals by predetermined coefficients h(0) to h(n-1);
3 adds the outputs of the multipliers 21 to 2n to obtain an output signal y(
This is an adder that outputs n).

Although this acyclic digital filter has n stages, for example, in order to equalize a sufficiently low frequency band to a desired characteristic, it is necessary to increase its order (number of stages) considerably.

When a single digital signal processing circuit (DSP) is insufficient in order to obtain desired frequency characteristics to configure an acyclic digital filter, a plurality of DSPs are continuously connected.

FIG. 4 is a block diagram showing an example of a conventional configuration in which a digital equalizer is configured using a plurality of DSPs in this manner.

In the same figure, 51 to 5m are cascade-connected DSPs.
and each of them is a delay circuit 6 as shown in FIG.
1 to 6M, multipliers 71 to 7 (M+l), adder 81
The filter is a part of an acyclic digital filter having the structure shown in FIG. 3 as a whole. 41 is DSP51
The ROM 42, in which the coefficients used in 5m to 5m are stored in advance, is a transfer means made of, for example, a microcomputer.

The transfer means 42 divides and reads out a series of coefficients necessary for the processing of the acyclic digital filter from the ROM 41.
If necessary, the contents are subjected to appropriate calculations or rearranged, and then sequentially supplied to each DSP 51 to 5m. Each DSP 51 to 5m processes the input signal in accordance with the supplied coefficients and sequentially outputs it to the next stage. As a result, a signal equalized to a desired frequency characteristic is output from the final stage DSP 5m.

[Problem to be solved by the invention]

In this way, traditional digital equalizers.

Since the contents stored in the ROM 41 are transferred to the DSPs 51 to 5m while being subjected to necessary arithmetic processing by the transfer means 42 consisting of a microcomputer, etc., there is a drawback that it takes time to transfer the contents. Ta.

As a result, when continuously input audio signals are being equalized and output, changing or adjusting the equalization characteristics requires the transfer of new coefficients. Occasionally, noise and sound dropouts were a problem.

The present invention was made in view of this situation, and is intended to shorten the transfer time and minimize the time for noise and sound interruptions.

[Means to solve the problem]

The digital equalizer of the present invention includes a plurality of cascade-connected digital signal processing circuits constituting an acyclic digital filter, and a first digital equalizer that stores the coefficients of the acyclic digital filter or the program code of the digital signal processing circuit. a second memory whose total capacity is equal to or greater than the number of coefficients or program code words; 1 transfer means.

and second transfer means for transferring the contents of the second memory to a corresponding digital signal processing circuit.

[Effect]

In the digital equalizer with the above configuration, for example,
The contents of the first memory are temporarily transferred to the second memory by a first transfer means such as a microcomputer. Then, the second transfer means transfers the signal from the second memory to the digital signal processing circuit.

Therefore, for example, a DMA controller or the like can be used as the second transfer means, and the transfer time can be shortened.

[Embodiment] FIG. 1 is a block diagram showing the configuration of an embodiment of the digital equalizer of the present invention, and the same reference numerals are given to the requirements corresponding to those in the conventional case.

In FIG. 1, reference numeral 61 denotes a first transfer means consisting of, for example, a microcomputer. 71 to 7m is
This is a RAM provided corresponding to the DSPs 51 to 5m, and stores the contents read from the ROM 41 by the first transfer means 61. 8 is a second transfer means consisting of, for example, a DMA controller, and has RAMs 71 to 7m.
The contents are sequentially transferred to the corresponding DSPs 51 to 5m.

Next, its operation will be explained.

The first transfer means 61 transfers the data stored in the ROM 41 to
Read out the coefficients corresponding to SP51 to 5m, and
After adding the necessary arithmetic processing to arrange the data into a format that can be transferred as is, the RAM corresponding to each DSP51 to 5m is
71 to 7m. The contents stored in RAM T1 to 7m are transferred to the corresponding DS by the second transfer means 8.
It is sequentially transferred to P51 to P5m.

The DSPs 51 to 5m follow the transferred coefficients.
The input audio signals are subjected to product-sum operations and sequentially output to the next stage. As a result, the final stage DSP 5m outputs a signal that is finally equalized to have the desired frequency characteristics.

Although a microcomputer or the like is used as the first transfer means 61, as the second transfer means 8.

Simple and fast means such as a DMA controller are used. Therefore, it takes the same time to transfer from ROM41 to RAM71 to RAM7m as in the conventional case, but
Transfer from 1 to 7 m to DSP 51 to 5 m can be performed in a short time. In reality, noise and sound interruptions occur during the transfer from RAM 71 to 7m to DSP 51 to 5m, so the microcomputer etc.
The transfer time can be shortened compared to the case of direct transfer from the ROM 41 to the DSPs 51 to 5m.

FIG. 2 is a block diagram showing the configuration of another embodiment of the digital equalizer of the present invention.

In this embodiment, the second transfer means 8 in the embodiment of FIG.
A plurality of them (m pieces) are provided corresponding to the SPs 51 to 5m and the RAMs 71 to 7m.

The other configurations are the same as in FIG. 1.

In the embodiment of FIG. 2, from RAM 71 to 7m, D
Coefficients can be transferred in parallel to SPs 51 to 5m. Therefore, it becomes possible to further shorten the transfer time.

In the above description, it is assumed that the coefficients of the acyclic digital filter are stored in the ROM 41, but the present invention is also applicable to the case where the program code of the DSP 51 to 5m realizing the acyclic digital filter is stored. is possible.

Furthermore, in the above description, the RAMs 71 to 7m do not necessarily have to be individual RAMs, but, for example, one large-capacity RAM.
It is clear that the AM may be used by dividing it into a plurality of blocks corresponding to the DSPs 51 to 5m.

〔Effect of the invention〕

As described above, according to the digital equalizer of the present invention, the contents of the first memory are transferred to the second memory by the first transfer means, and the contents of the second memory are transferred to the digital signal by the second transfer means. Since the data is transferred to the processing circuit, it is possible to use a device that operates at high speed as the second transfer means, and it is possible to shorten the transfer time from the first memory to the digital signal processing circuit.

Therefore, especially when changing the equalization characteristics of a low frequency signal, it is possible to significantly shorten the time during which noise or sound breaks occur.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the digital equalizer of the present invention, FIG. 2 is a block diagram showing the configuration of another embodiment of the digital equalizer of the present invention, and FIG. 3 is a block diagram showing the configuration of another embodiment of the digital equalizer of the present invention. FIG. 4 is a block diagram showing the structure of an example of a conventional digital equalizer. FIG. 5 is a block diagram showing the structure of a part of a divided acyclic digital filter. be. 11 to in...delay circuit, 21 to 2n...multiplier, 3...adder, 41...ROM, 42...transfer means, 51 to 5n...digital signal processing circuit,
61...first transfer means, 71 to 7 m-RAM
, 8.81 to 8m...second transfer means.

Claims (1)

[Scope of Claims] A plurality of cascade-connected digital signal processing circuits constituting an acyclic digital filter, and a first circuit that stores coefficients of the acyclic digital filter or program codes of the digital signal processing circuit. a number of second memories corresponding to the number of digital signal processing circuits, the total capacity of which is greater than the number of words of the coefficients or program code; A digital equalizer comprising: first transfer means for transferring to a memory; and second transfer means for transferring contents of the second memory to the corresponding digital signal processing circuit.