JPH0361332U - - Google Patents
Info
- Publication number
- JPH0361332U JPH0361332U JP1989121686U JP12168689U JPH0361332U JP H0361332 U JPH0361332 U JP H0361332U JP 1989121686 U JP1989121686 U JP 1989121686U JP 12168689 U JP12168689 U JP 12168689U JP H0361332 U JPH0361332 U JP H0361332U
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- diffusion layer
- type diffusion
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims 1
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 2
Landscapes
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図ａ１〜ｃ１は本考案に係る半導体装置の
製造工程を示す平面図、第１図ａ２〜ｃ２はそれ
ぞれ第１図ａ１〜ｃ１のＡ−Ａ線における断面図
、第２図は本考案に係る半導体装置の等価回路図
、第３図ａ及びｂ、第４図ａ〜ｃは従来の半導体
装置を説明するための各製造工程における平面図
である。
２２……第１コンタクトホール、２４……第２
コンタクトール、２５……中間絶縁膜、２６……
ゲート電極、２７……フイールド酸化膜、２８…
…ＷＳｉ配線、２９……絶縁膜、３０……Ａｌ−
Ｓｉ配線。
1A1 to C1 are plan views showing the manufacturing process of a semiconductor device according to the present invention, FIGS. 1A2 to C2 are sectional views taken along line A-A in FIGS. 1A1 to C1, respectively, and FIG. 3A and 3B and FIGS. 4A to 4C are plan views in each manufacturing process for explaining the conventional semiconductor device. 22...first contact hole, 24...second
Contactor, 25... Intermediate insulating film, 26...
Gate electrode, 27...Field oxide film, 28...
...WSi wiring, 29...Insulating film, 30...Al-
Si wiring.
Claims (1)
ランジスタを具えかつこれらトランジスタのｐ型
拡散層及びｎ型拡散層間に配線を具える半導体装
置において、 前記配線をタングステンシリサイドＷＳｉを以
つて構成したことを特徴とする半導体装置。[Claims for Utility Model Registration] A semiconductor device comprising a pMOS transistor and an nMOS transistor, and a wiring between a p-type diffusion layer and an n-type diffusion layer of these transistors, wherein the wiring is made of tungsten silicide WSi. A semiconductor device characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989121686U JPH0361332U (en) | 1989-10-19 | 1989-10-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989121686U JPH0361332U (en) | 1989-10-19 | 1989-10-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0361332U true JPH0361332U (en) | 1991-06-17 |
Family
ID=31669712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989121686U Pending JPH0361332U (en) | 1989-10-19 | 1989-10-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0361332U (en) |
-
1989
- 1989-10-19 JP JP1989121686U patent/JPH0361332U/ja active Pending
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