JPH0361336U - - Google Patents

Info

Publication number
JPH0361336U
JPH0361336U JP1989120989U JP12098989U JPH0361336U JP H0361336 U JPH0361336 U JP H0361336U JP 1989120989 U JP1989120989 U JP 1989120989U JP 12098989 U JP12098989 U JP 12098989U JP H0361336 U JPH0361336 U JP H0361336U
Authority
JP
Japan
Prior art keywords
metal film
coated
wiring
grounded
electronic components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989120989U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989120989U priority Critical patent/JPH0361336U/ja
Publication of JPH0361336U publication Critical patent/JPH0361336U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01515—Forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案の実施例を示す配線基板の配線
工程断面図、第２図は従来のワイヤボンド接続さ
れた配線基板の断面図、第３図は第２図の配線基
板の平面図である。 １０……基板、２０……配線パターン、３０…
…ＩＣ、４０……ワイヤ、５１……絶縁膜、６１
……Ｎｉ−Ｗ−Ｐ膜。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 電子部品を実装する配線基板において、 電子部品と基板との配線部分を絶縁膜でコーテ
    イングし、更に金属膜でコーテイングし、該金属
    膜を接地するようにしたことを特徴とする配線構
    造。 (2) ＩＣチツプ、ＳＡＷフイルタチツプ等の電
    子部品を搭載したケースから導出されるリード線
    を絶縁膜でコーテイングし、更に金属膜でコーテ
    イングし、該金属膜を接地するようにしたことを
    特徴とする配線構造。
JP1989120989U 1989-10-18 1989-10-18 Pending JPH0361336U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989120989U JPH0361336U (ja) 1989-10-18 1989-10-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989120989U JPH0361336U (ja) 1989-10-18 1989-10-18

Publications (1)

Publication Number Publication Date
JPH0361336U true JPH0361336U (ja) 1991-06-17

Family

ID=31669037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989120989U Pending JPH0361336U (ja) 1989-10-18 1989-10-18

Country Status (1)

Country Link
JP (1) JPH0361336U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007290770A (ja) * 2006-04-27 2007-11-08 Sekisui Plastics Co Ltd 保冷容器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0217840B2 (ja) * 1983-10-07 1990-04-23 Tokyo Denryoku Kk

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0217840B2 (ja) * 1983-10-07 1990-04-23 Tokyo Denryoku Kk

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007290770A (ja) * 2006-04-27 2007-11-08 Sekisui Plastics Co Ltd 保冷容器

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