JPH0362145A - Memory controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention particularly relates to a memory control device used in a fault-tolerant computer system.

(Prior art) Conventionally, in fault-tolerant computer systems, in order to increase the reliability of the system, even if a part of the system fails, it maintains a state that appears to be functioning normally from the outside. Various methods have been adopted for this purpose.

In such a system, a method of configuring the memory modules redundantly may be considered in order to obtain a fault tolerance function of the system when a failure occurs in the memory module. However, when memory modules are configured redundantly, it is necessary to access the same address of a plurality of memory modules, but when there is only one memory bus, accessing the same address is impossible.

(Problem to be solved by the invention) In a fault-tolerant computer system, if there is only one memory bus, simply configuring memory modules redundantly makes it impossible to access the same address in each memory. .

This provides a fault tolerance of 8! for memory modules. & It was difficult to play Noh to the 11th level.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control device that enables a redundant configuration of memory modules even when there is only one memory bus, and can provide a large fault tolerance function for the memory modules.

[Structure of the Invention] (Means and Works for Solving the Problems 111) The present invention provides a memory control device used in a 3.1 computer system with a fault tolerance This device enables a data copy function using a single memory bus in contrast to a dual-configuration memory means that floats data.This device transfers the same data stored in the master side memory to the slave side memory. A first copy means that writes the same data to the slave memory at the same address as the address of the master memory during the copy mode, and a write that writes new data to the master memory during the copy mode. and second copying means for copying new data written in the master side memory to the slave side memory at the same address in the mode.

(Large box fF1) The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a memory system according to the same embodiment. As shown in FIG. 1, a plurality of first and second memory modules 10a and 10b, one of which is used as a master side memory and the other used as a slave side memory.
is provided. Each memory module IOa, l
Ob is an area lla for storing information indicating whether the memory is a master side memory or a slave side memory.
, llb are provided. Each memory module
Oa and lOb are connected to each other through a common memory bus 12.
Transfer of data and addresses takes place.

The memory control unit 13 controls each memory module l0alOb.
A data register 14 and an address register 15 are provided for reading/writing data to/from the memory.

Furthermore, the memory control unit 13 controls each memory module IOa.
, lOb are provided with flip-flops 16 and 17 for setting flags necessary for a copy operation of writing the same data to the same address.

Flip-flop (F/F) 1 (i sets a flag indicating whether the memory module (10a or 10b) with access χ1 is master side memory (“0”) or slave side memory (“1”) The flip-flop 17 is connected to each memory module IO.
This is a circuit for setting a flag indicating whether the IOb is in dual write mode, cell or permission state.

The CPU 20 is a central processing unit that operates based on a predetermined program, and communicates with each memory module through the system bus 18! Oa, data ratio for lOb/
Run the light. The DMA 21 is a direct memory access device, and reads/writes data to/from each memory module 10a, 10b via the system bus 18.

Next, the operation of this embodiment will be explained.

First, as shown in step S1 of FIG.
A copy command for executing the copy mode is output to the memory control unit 13 from. In the memory control unit 13,
In order to access the memory module lOa, which is the master side memory, a flag 'O'' is set in the F/FIB (step S2).

The memory control unit 13 controls the master side memory module tO.
A predetermined address of a is accessed and data corresponding to that address is read. The memory control unit 13 stores the read data in the data register 14, and stores the address at that time in the address register 15 (step S3).

Next, the memory control unit 13 executes a copy operation to write the read data to the memory module lOb, which is the slave side memory. The memory control unit 13 is F/F1
A flag 11 is set in B, and address data obtained by adding the flag 1'' to the address stored in the address register 15 is output to the memory bus 12 (step S4).

As a result, the memory module IOb on the slave side is accessed, and the same address as the memory module loa on the master side is accessed. The memory control unit 13 transfers and stores the data stored in the data register 14 to the same address of the accessed slave-side memory module lob (step S5).

That is, the memory module 10b on the slave side has the same address as the memory module 10a on the master side.
The data will be copied.

Now, suppose that a write mode interrupt to write data to the master side memory module loa is made from the CPU 2G during the copy mode as described above (
Step S6. S7). CPU 20 is system bus 18
The write data is transferred to the memory control unit 13 through the memory control unit 13. The memory control unit 13 stores the transferred write data in the data register 14 (step S8). moreover,
The memory control unit 13 controls the master side memory module lQ.
In order to access a, the flag 0'' is set in the F/FIB (step S9). 12, and accesses a predetermined address of the memory module IOa on the master side. The write data stored in the data register 14 is transferred and written to the predetermined address of the accessed master-side memory module lOa (step 510).

On the other hand, since the write mode is before the completion of the copy mode (that is, in the copy mode), the memory control unit 13 transfers the new data (write data) written to the memory module IOa on the master side to the memory module IOa on the slave side.
Execute the operation to copy to Ob. That is, the memory control unit 13 sets a flag 1” in the F/F 16 in order to access the memory module tab on the slave side (step 512). flag 1 for the address of
" is added to the address data is output to the memory bus 12, and the same address as the predetermined address of the memory module lOa on the master side is accessed.The predetermined address of the accessed memory module tab on the slave side is
The new data stored in the data register 14 is transferred and written (step 513). At this time,
The memory control unit 13 controls each memory module lOa,
A flag (for example, "1") indicating whether the dual write mode is permitted for the flip-flop 10b is set in the flip-flop 17 (step 514). In this case, c
When a dual write mode prohibition command is transferred from ptr2o, the memory control unit 13 sets a flag (for example, "0') indicating whether the dual write mode is in a prohibited state to the flip-flop 1.
Set to 7. When the interrupt write mode ends, the copy operation is started again, and the processing of steps 82 to S5 is continued until the copy operation is completed.

In this way, the same data can be copied from the master side memory module 10a to the slave side memory module lOb at the same address. Therefore, it is possible to realize a redundant configuration of a plurality of memory modules that perform the same function. Thereby, if the master side memory module IOa fails, the slave side memory module tab can be used as the master side memory, and the same data can be accessed from the same address. In other words, it is possible to implement a fault tolerance function for the memory module.

In this case, in the present invention, by using the flip-flop 16 for identifying the master side and the slave side, it is possible to access the same address of each memory on the master side and slave side using one memory bus 12. I can do it. In other words, a dual configuration memory system can be realized using one memory bus 12.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to realize a memory system with a dual configuration and a redundant configuration using one memory bus. Therefore, if the present invention is applied to a fault-tolerant computer system, the fault-tolerant function for the memory system can be greatly realized, and the reliability of the entire system can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a memory system according to an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of the embodiment. 10a, IOb... memory module, 13...
・Memory control unit, 14...Data register, 1B...
・Flip-flop, 20...CPU.

Claims (2)

[Claims] (1) A dual configuration memory means in which one side is used as a master side memory and the other side is used as a slave side memory, and in a copy mode in which the same data stored in the master side memory is copied to the slave side memory, the above a first copying means for writing the same data to the slave side memory at the same address as the address of the master side memory, and during a write mode during the period of the copy mode and writing new data to the master side memory; , a second one for copying the new data written to the master side memory to the slave side memory at the same address.
What is claimed is: 1. A memory control device comprising a copying means. (2) A dual configuration memory means in which one side is used as a master side memory and the other side is used as a slave side memory, and when accessing the same address of the master side memory and the slave side memory, the same address is used. an identification means for identifying the relevant memory; and an address of the master side memory in a copy mode for copying the same data stored in the master side memory to the slave side memory based on the identification result of the identification means; a first copying means for writing the same data to the slave side memory at the same address as the master side memory; and a first copying means for writing the same data to the slave side memory at the same address as the first copying means; register means for temporarily storing the data; and writing the new data stored in the register means into a master side memory, reading this new data from the register means, and writing the new data stored in the register means to the slave side at the same address as the master side memory. A memory control device comprising: second copying means for copying to memory.