JPH0364066A - Manufacture of bipolar cmos semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a semiconductor integrated circuit, and particularly to a bipolar CH in which a bipolar element and an 0MO3 element are formed on the same substrate.
The present invention relates to a method for manufacturing an O5 (hereinafter abbreviated as Bi CMO3) type semiconductor integrated circuit.

(Prior Art) In recent years, Bi CMO5 mixed mounting technology has been increasingly used for the purpose of increasing the speed of analog/digital mixed mounting and 0MO5, and this has become the mainstream in the field of composite technology.

AtC QSLSI (bipolar CMOS semiconductor integrated circuit) combines the features of bipolar and CMOS devices, so it achieves excellent performance such as high speed, high integration, high voltage resistance, high load driving ability, and low power consumption. Although it is possible,
Structurally, an epitaxial layer and isolation diffusion are required to mount a bipolar element.

Further, the process for simultaneously forming bipolar elements and CMOS elements without impairing their performance is complicated, and the number of masks increases, which is disadvantageous from an economic point of view.

Here, a conventional Bi CMO3 type semiconductor integrated circuit will be explained with reference to the drawings.

FIG. 2 is a sectional view showing the overall structure of such a conventional Bi CMO5 type semiconductor integrated circuit.

As shown in this figure, an N buried diffusion layer 2 is formed in a P- type semiconductor substrate 1, and the N4 buried diffusion layer 2 is an N buried diffusion layer 2.
To lower the collector series resistance of N Bi Trloo, it is usually diffused with As or SB to 20-100 Ω/port. Incidentally, a method for manufacturing the NPN Bi TrlOO portion is disclosed in JP-A-63-102259. Further, in order to prevent the PMO 3300 from causing parasitic bipolar operation, N2 buried diffusion N2 is also simultaneously diffused into the PMO 3300 type region.

The P isolation diffusion layer 3 is formed in advance in the element isolation region of the NPN Bt Tr 100 by an ion implantation method, etc., and prevents upward diffusion from the P- type semiconductor substrate 1 during the epitaxial layer formation and isolation diffusion in the next process. It is used to shorten the separation and diffusion time by utilizing B(
Boron) is used to set the resistance to 50 to 300Ω/mouth. Also here, in order to prevent the NHO 2200 from causing a parasitic bipolar operation, the P isolation diffusion layer 3 is simultaneously formed in the NHO 2200 formation region.

The N-type epitaxial layer 4 is NPN Bi Tr 1
Its concentration and thickness are determined so that the device characteristics of PMO 5300 and the gate threshold voltage of PMO 5300 can be controlled. 5 is a P-diffusion region.

The P diffusion N6 forms the active base of the NPN Bt Tr 10(l), and the P diffusion region 7 forms the active base of the NPN Bt Tr 10
0 source/drain and NPN Bi Tr 100
forming an inactive base layer. This inactive base layer is necessary to make regular contact to the base layer.

Further, the N diffusion layer 8 forms a contact extraction layer for the source/drain of NHO 2200 and the emitter/collector layer of NPN Bi Tr 100.

The P diffusion layer 6, the P'' diffusion region 7, and the N'' diffusion layer 8 are selectively diffused using the oxide film IO as a mask so as to form P, P", and N" wi regions, respectively. In addition, 9 is PM
O5300, N? This is the gate of IO3200.

In this way, a Bt CMO3 type semiconductor integrated circuit is constructed, but the steps after forming the epitaxial layer only include the active base layer forming step in addition to the normal CMO5 manufacturing process, and most of them are formed at the same time. It has become. Therefore, in order to pursue economic efficiency in the manufacturing process of Bi CMO3 type semiconductor integrated circuits, it is essential to simplify the process before forming the epitaxial layer.

(Problem to be Solved by the Invention) However, in the above manufacturing method, N'' buried diffusion N
2 and the P isolation diffusion layer 3 are adjacent to each other without a gap, so the junction breakdown voltage is as low as 1O-15V.For example, the breakdown voltage (BVCEO) of BiTr is 4.
A high breakdown voltage transistor of about 0V is made of Bi of Bt CMO3 element.
When formed as a Tr on the P-type semiconductor 111, Bt
Before the Tr breaks down at 40V, the junction breakdown voltage between the N° buried diffusion layer 2 and the P° isolation diffusion II 3 is 10 to 1.
There was a problem in that the element breakdown voltage was determined at about 5V.

In order to solve this problem, there is a Bi CMO3 type semiconductor integrated circuit having a cross-sectional structure as shown in FIG. To form this, it is necessary to repeat the cycle of thermal oxidation, photolithography/etching, and annealing twice, which increases the number of steps and takes a longer time.

■Since the misalignment of layers must be taken into consideration, N°
The distance between the buried diffusion layer 22 and the P isolation diffusion layer 24 must be larger than necessary.

There was a problem.

In this figure, 21 is a P-type semiconductor substrate, 25 is
is an N-epitaxial layer, 26 is an NPN Bi Tr
This is a P diffusion layer forming the active base of 400.

The P diffusion region 27 forms the source/drain of the PMO 3600 and the inactive base layer of the NPN Bi Tr 400. 28 is a N diffusion layer, NHO2
500 source/drain and NPN 84 Tr 4
00 emitter/collector layer contact extraction layer is formed. Also, 29 is P well, 30 is N well, 31
32 is an oxide film, 32 is an AI electrode, and 33 is a gate.

As described above, the present invention has the following advantages: (1) As shown in FIG. 2, the N'' buried layer and the P+ buried layer collide with each other, resulting in a low junction breakdown voltage.

(2) As shown in FIG. 3, if the distance between the N-containing layer and the P-containing layer is widened, (1) the number of steps increases and the processing time becomes longer.

■The element size becomes larger because of the misalignment of layers.

In order to eliminate such problems, N゛buried layered region P°buried layered region is formed using one mask, and
Since annealing is performed on both the N-filled layer and the P-filled layer at the same time, the process can be shortened even if the distance between the N-filled layer and the P-filled layer is widened, and misalignment of the layers can be avoided. An object of the present invention is to provide a method for manufacturing a bipolar CMO3 type semiconductor integrated circuit having a high breakdown voltage element.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides bipolar CM
A method for manufacturing an O5 type semiconductor integrated circuit includes a step of forming a SiO1 film over the entire surface of a first conductivity type St substrate, and then forming a Sizes film on the Sing film, and forming a first conductivity type impurity layer and a second conductivity type impurity layer. The Sis in the region where the conductive impurity layer is formed
a step of forming a first conductivity type glass on the first conductivity type impurity layered region after simultaneously removing the Ni MA;
The steps of etching and removing the 5kOt film on the conductive impurity layer region, ion-implanting the second conductive impurity, and forming a diffusion layer by annealing are performed in this order. It is something.

(Function) As described above, in the method of manufacturing a Bi CMO3 type semiconductor integrated circuit, the present invention forms an Si0g film on the surface of a Si substrate, forms an SiJa film on the stow film, and then
The Si3N film in the part that will become the buried layer and the P" buried layer is removed, and FISG is formed on the entire surface. Next, the BSG and Sift film in the part that will become the N" buried layer are removed, and the sb implant is removed. An N-type impurity (Sb) for forming an N buried layer is formed on the surface of the Si substrate. Therefore, Bi 0 for high voltage
As an MO3 substrate, the number of steps can be reduced despite the distance between the N4 buried layer and the P00 buried layer.
Moreover, since the N0 buried layer and the P99 buried layer need only be spaced apart enough to obtain the target breakdown voltage, there is no misalignment and the chip area can be reduced.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing the manufacturing process of a bipolar CMO5 type semiconductor integrated circuit showing an embodiment of the present invention.

In the following explanation, the steps up to the epitaxial growth step will be explained in detail, and the element forming steps after the epitaxial formation will be briefly explained because they are the same as those in the prior art.

(1> First, as shown in FIG. 1(a), 500 SiO□ films 42 are deposited on a P-type semiconductor (Si) substrate 41, and then a SiO film is deposited using the known 17) CVD method. 42
3000 layers of SiiNa film 43 are formed on the top.

(2> Next, using known photolithography and etching techniques, as shown in FIG.
The SisN* film 43 and the Sift film 42 in the portions that become the depressed layer and their boundary regions are removed at the same time. in this case,
If the distance between the N-type layer and the P-type layer is about 16 pm, a breakdown voltage of IIQ V can be obtained.

(3) Next, after forming a BSGS electrical film on the entire surface of the P-type semiconductor substrate 41, using known photolithography and etching techniques, as shown in FIG. territory B
Remove the SGS film. Then eV to 40, 2XI
SB ion implantation 46 is performed under the condition of OIs ions/d to form a N0 layer for 4 days.

(4) Next, use Ar ・Ox gas to
, a 3-hour drive-in is performed to form an N4 layer 48 and 14 layers 49 by diffusion from BSG 11145, as shown in FIG. 1(d).

(5) After the drive-in is completed, BSG 11145. Si
sN411143, stow film 42 and 2 on the film were removed,
As shown in FIG. 1(e), an N epitaxial layer 50 is formed on a P- type semiconductor substrate 41. As shown in FIG.

Since the subsequent steps are similar to those of the prior art, they will be briefly explained.

(6> After forming the N epitaxial layer 50, FIG. 1(f)
As shown in FIG.
P wells 52 are formed in the O3 type tceI regions.

(7) Next, a SisNa film is deposited, and as shown in FIG. 1(g), the 5LsNa film 53 is
LOGO5 is oxidized while leaving the oxide film 54.

(8) Next, after removing the Si3N film 53, Fig. 1 (h)
As shown in , the base type tc 8 of NPN Bi Tr
B (boron) 55 is implanted into the first region to form a second layer 56.

(9) Next, after forming polycrystalline silicon on the entire surface, NHO2
As shown in FIG. 1(i), a gate 57 made of polycrystalline silicon is formed on the portion that will become the gate using known photolithography and etching techniques.

(10) Next, as shown in Figure 1 U), NPN Bi
In common with the collector and emitter of Tr, NrlO3
As as an N0 impurity in the source/drain region
(Arsenic) 58 is ion-implanted to form an N4 layer 59.

(11> Next, as shown in Figure 1(k), PMO5
B(
Boron) 60 is implanted to form a P layer 61.

(Step 2) Finally, a wiring layer is formed, patterned using photolithography and etching technology, and NPN Bt Tr
700.

NHO 5800 and PMO 3900 are each formed to complete a bipolar CMO5 type semiconductor integrated circuit as shown in FIG. 1(1).

Note that instead of the NPN Bi Tr in the above embodiment, a PNP Bi Tr may be formed, and furthermore, another Bl element, such as a resistance element, may be formed.

Furthermore, the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(Effects of the Invention) As described in detail above, according to the present invention, the P'' buried layer type area N'' buried layer type area is formed using the same photomask, and these buried layer type areas are formed using the same photomask. Since the diffusion of the buried layer is performed in the same heat treatment, even though the distance between the N'' buried layer and the P'' buried layer is kept as a high voltage Bi CMO3 substrate, (1) the number of steps is reduced. can be reduced.

(2) Since the N''''-containing layer and the P''tl-containing layer need only be spaced apart enough to obtain the target breakdown voltage, there is no misalignment and the chip area can be reduced.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the manufacturing process of a bipolar CMO5 type semiconductor integrated circuit showing an embodiment of the present invention, and FIG.
FIG. 3 is a sectional view showing the overall structure of a CMOS type semiconductor integrated circuit. FIG. 3 is a sectional view showing the overall structure of another conventional Bi CMOS type semiconductor integrated circuit. 41...P-type semiconductor (Si) substrate, 42...Si
0g film, 43°53...SiJ, film, 45...BS
G film, 48.59...N° layer, 49°61...14
layer, 50...N epitaxial layer, 51...N well, 52...P well, 57... gate.

Claims (1)

[Claims] (a) After forming an SiO_2 film on the entire surface of the first conductivity type Si substrate, forming a Si_3N_4 film on the SiO_2 film; (b) forming the first conductivity type impurity layer and the first conductivity type impurity layer; (c) forming a first conductivity type glass on the first conductivity type impurity layer formation region after simultaneously removing the Si_3N_4 film in the region where the second conductivity type impurity layer is to be formed; The S on the type impurity layer forming region
A bipolar CMOS type characterized in that a step of etching away the iO_2 film, (d) a step of ion-implanting the second conductivity type impurity, and (e) a step of performing annealing to form a diffusion layer are performed in order. A method for manufacturing semiconductor integrated circuits.