JPH0366132A - Bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE:To form a base layer having a prescribed shape and a prescribed size with good reproducibility even when the base layer is thinned by a method wherein, after a base electrode has been formed, an emitter layer is formed. CONSTITUTION:An n-GaAs collector layer 2 as a first semiconductor layer is formed on a substrate 1; a p-GaAs base layer 3 as a second semiconductor layer is formed on one part on it. Base electrodes 4 composed of a metal layer are formed in partial parts on the base layer 3; surfaces and side faces of the base electrodes 4 are covered with insulating layers 5 and insulating-film sidewalls 6. In addition, an n-AlGaAs emitter layer 7 as a third semiconductor layer is formed so as to come into contact with a residual part of the base layer 3. Thereby, since the second semiconductor layer is exposed, it is not required to etch the third semiconductor layer. As a result, even when the second semiconductor layer which is thin is used, the second semiconductor can be formed with good reproducibility.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bipolar transistor and a method for manufacturing the same, and particularly to a method for making a base layer thin and forming a base electrode with good reproducibility on the base layer. The present invention relates to a bipolar transistor having a structure that can be used as a bipolar transistor, and a method for manufacturing the same.

(Prior Art) FIG. 3 is a sectional view showing the structure of a typical conventional heterojunction bipolar transistor. In the same figure, board (1)
An n-type (hereinafter referred to as n-) GaAs:ff collector layer (2) is formed on top, and the n-GaAs collector layer (
-2) A p-type (hereinafter referred to as p-) GaAs base layer (3) is formed on top. Furthermore, on the pGaAs base layer (3), there is a base electrode (4) and an nAjlGaAs layer.
An emitter layer (7) is formed. n-AjlGaA
An emitter electrode (8) is formed on the s emitter layer (7), and a collector electrode (9) is formed on the n-GaAs collector layer (2).

In the above bipolar transistor, the main current flows from the emitter electrode (8) to the n-AUGaAs emitter layer (7), the p-GaAs base layer (3), and the n-AUGaAs emitter layer (7), and the n-AUGaAs base layer (3).
-GaAs collector layer (2) to the collector electrode, but as is well known, this main current flows from the emitter electrode (8) to the n-AUGaAs ivy layer (7) and p
- Controlled by a minute signal current flowing through the GaAs base layer (3) to the base electrode (4).

The manufacturing process of the conventional bipolar transistor shown in FIG. 3 will be explained with reference to FIG. 4.

■As shown in Figure 4(a), first place the n on the substrate (1).
-GaAs collector layer (2), p-GaAs base layer (31), and n-AJ2GaAs ivy layer (71) are sequentially deposited.

(2) Next, as shown in FIG. 4(b), an emitter electrode metal layer (81) is formed at a predetermined position on the n-AUGaAs emitter layer (71) by a lift-off method.

(2) Next, as shown in FIG. 4(C), the metal layer (81) for the vine electrode is used as a mask.

A part of the AUGaAs emitter layer (71) is etched to form n-Aj! of a predetermined shape. GaAs emitter layer (7
) to form.

■Next, the p-GaAs base layer (31) in Figure 4(C)
Then, a resist is applied on the emitter electrode metal layer (81) and burned to leave a base electrode lift-off resist (41) as shown in FIG. 4(d).

■Next, the p-GaAs base layer (31
), the metal layer for the ivy electrode (81), and the resist for the base electrode lift-off (41) are deposited on the entire surface, and the base electrode (4) as shown in FIG. 4(e) is formed by the lift-off method. form. At this time, a metal layer (82) is also deposited on the metal layer (81) for the ivy electrode, so the emitter electrode (8) is formed by the metal layer (81) for the emitter electrode and the metal layer (82). be done.

(2) Next, a resist is applied to the entire surface of FIG. 4(e) and buttered, leaving a collector electrode lift-off resist (42). Then, using this resist (42) as a mask, a part of the p-GaAs base layer (31) is etched to form a predetermined shape of p-GaAs as shown in FIG. 4(f).
An aAs base layer (3) is formed and a portion (21) of the n-GaAs collector layer (2) is exposed.

(2) Finally, a metal layer for a collector electrode is deposited on the entire surface of FIG. 4(f), and a collector electrode (9) is formed by a lift-off method to complete the bipolar transistor having the structure shown in FIG. 3.

(Problem to be Solved by the Invention) In the conventional heterojunction bipolar transistor described above, n -AUGaA is used to form the base electrode (4).
Part of the s emitter layer (71) is etched to form pGaA
It is necessary to expose the s base layer (31) (see Figure 4 (
c)) Since the p-GaAs base layer (31) is very thin, usually less than 1000 Å, the above nA
Etching of the 11GaAs emitter layer (71) requires extremely high precision etching. For this reason, in the conventional bipolar transistor, there was a problem that the reproducibility of the base layer (31) was poor. p-GaA is needed to improve the performance of heterojunction bipolar transistors.
Although it is necessary to make the s-base layer (3) and therefore (31) thinner, there is a limit to how thin it can be made for the above reasons, and a significant improvement in performance could not be expected.

(Means for Solving the Problems) The heterojunction bipolar transistor according to the present invention includes a first semiconductor layer of one conductivity type (for example, n-GaAs A second layer of the other conductivity type formed on a part of the collector layer 2)
a semiconductor layer (for example, p-GaAs base layer 3), a metal electrode (base electrode 4) formed on a part of the second semiconductor layer in contact with the second semiconductor layer, and a top and side surface of the metal electrode. an insulating film (5, 6) formed over the metal electrode, a part of which is formed on the second semiconductor layer in contact therewith, and the remaining part formed on the insulating film that covers the metal electrode. 3rd r of force conduction η1: conductor e.g. n-AAGaAs
an emitter layer 7), a metal electrode formed on the third semiconductor layer in contact with it (a metal electrode 8), and a metal electrode formed in contact with the first semiconductor layer ( It has a collector electrode 9).

[For production]

According to the bipolar transistor having the above structure, it is not necessary to etch the third semiconductor layer (n/1 GaAs base layer 7) in order to expose the second semiconductor layer (P-GaAs base layer 3). Therefore, even if a thin second semiconductor layer is used, the second semiconductor layer can be formed with good reproducibility, and the performance is significantly improved.

(Example) Hereinafter, a heterojunction bipolar transistor of the present invention and a method for manufacturing the same will be explained with reference to FIGS. 1 and 2.

FIG. 1 is a sectional view showing an embodiment of a heterojunction bipolar transistor according to the present invention.

Components of the bipolar transistor shown in FIG. 1 that are equivalent to those of the conventional bipolar transistor shown in FIG. 3 are given the same reference numerals. In the figure, a substrate (1)l has a first semiconductor layer, for example, n-Ga.
An As collector layer (2) is also formed. Collector layer (
2) A second semiconductor layer, e.g. p-Ga, is formed on a part of the upper part.
A base layer (3) is formed on the top of the eighth layer, and a collector electrode (made of a metal layer) is formed on the other part of the collector layer (2).
9) is formed. A base electrode (4) made of a metal layer is formed on a part of the base layer (3), and two and side surfaces of the base electrode (4) are covered with an insulating layer (5) and an insulating film sidewall ( 6) covered by Further, an n-AJ2GaAs emitter layer (7), which is a third semiconductor layer, is in contact with the remaining portion of the base layer (3).
is formed, the end of which extends onto the insulating film (5) covering the base electrode (4). n-HeheGaA
An emitter electrode (8) made of a metal layer is formed on the ivy layer (7).

The manufacturing process of the bipolar transistor of the present invention shown in FIG. 1 will be explained with reference to FIG.

■As shown in Figure 2(a), nGaA is placed on the substrate (1).
s collector layer (2), p-GaAs base! (3
1) are sequentially deposited.

■Next, a metal layer (42) for forming a base electrode and an insulating film layer (51) are sequentially deposited on the p-Ga base W (31), and a resist is further applied on the insulating film layer (51). Then, patterning is performed to form a base electrode forming resist (21) as shown in FIG. 2(b).

■Next, the insulating film layer (51) and base layer (31) were etched and notched using the base electrode forming resist (21) as a mask, and were laminated in a predetermined shape as shown in FIG. 2(C). A base electrode (4) and an insulating film (5) are formed.

■Next, the resist (21) in FIG. 2(C) is removed to expose the insulating film (5), and the base electrode (0) is removed.
2(d) covering the side surfaces and the entire surface of the base layer (31).
), the second insulating film layer (61) is formed.

■Next, the second insulating film layer (61) is selectively etched with reactive ions to form an insulator covering the side surfaces of the base electrode (4) and the insulating film (5) as shown in FIG. 2(e). Form the membrane sidewall (6).

(2) Next, a J2Ga8S emitter vine layer (71) is formed on the entire surface of FIG. 2(e) as shown in 21'E(f).

■Next, a resist is applied to the entire surface of the emitter W (71) in FIG. 2(e) and patterned to form an emitter forming resist (22) as shown in FIG. 2(g). ) as a mask, a part of the emitter layer (71) and base layer (31) is etched using an etch center that does not etch the insulating film to form a vine layer (7) with a predetermined shape as shown in the figure. do.

(2) Next, a resist is applied to the entire surface as shown in FIG. 2(g) and patterned to form an emitter electrode and collector electrode lift-off resist (23) having a shape as shown in FIG. 2(h).

■Finally, electrode metal is deposited on the entire surface of Figure 2 (h), and the emitter electrode (
8), a collector electrode (9) is formed on the exposed portion of the collector layer (2), and the bipolar transistor 0 of the present invention having the structure shown in FIG. 1 is completed.

(Effects of the Invention) As described above, in the bipolar transistor of the present invention, after forming the base electrode (4), the emitter layer (7) is formed.
is formed, there is no need for a highly accurate etching process in which a part of the emitter layer formed on the entire surface of the base layer is removed by etching to expose the base layer as in conventional bipolar transistors. For this reason, the base layer (3
Even if 1) is made thinner than 1000 Å, it becomes possible to form a base layer (3) with a predetermined shape and dimensions with good reproducibility.
High performance bipolar transistors can be manufactured with high yield.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the main parts of an embodiment of the bipolar transistor according to the present invention, and FIGS. 2(a) to (h) are each manufacturing process for explaining the manufacturing process of the bipolar transistor according to the present invention shown in FIG. FIG. 3 is a sectional view of the main part showing an example of a conventional bipolar transistor, and FIGS. 4(a) to (f) explain the manufacturing process of the bipolar transistor of the present invention shown in FIG. 3. FIG. (2)...first semiconductor layer, (3)...second semiconductor layer, (4)...metal electrode, (5), (6)...
...Insulating film, (7)...Third semiconductor layer, (8)
, (9)...Metal electrode. Agent Masuo Oiwa 1 2 Procedures Draw Yuki (Voluntary) Urejima 2 years February 27, 3, Representative of the person making the amendment 5 ``Detailed description of the invention'' column of the specification to be amended. 6 Contents of Supplement M (1) “Base layer (31)” in page 9, line 10 of the specification
J is corrected as "Metal layer for base electrode formation (42) J." (2) In the same book, page 10, line 10, "etch cent" is changed to "
Echant” I corrected. I”d

Claims (2)

[Claims] (1) A first semiconductor layer of one conductivity type, a second semiconductor layer of the other conductivity type formed on a part of the first semiconductor layer, and a part of the semiconductor layer on the second semiconductor layer. a metal electrode formed on a portion in contact with the second semiconductor layer; an insulating film formed covering the top and side surfaces of the metal electrode; a portion formed on the second semiconductor layer in contact therewith; a third semiconductor layer of one conductivity type formed on the insulating film, the remaining portion of which covers the metal electrode; a metal electrode formed in contact with the third semiconductor layer; A bipolar transistor having a metal electrode formed in contact with a semiconductor layer. (2) forming a second semiconductor layer of the other conductivity type on the first semiconductor layer of one conductivity type; and contacting the second semiconductor layer at a predetermined position on the second semiconductor layer; a step of forming a metal electrode and forming an insulating film covering the top and side surfaces of the metal electrode, a part of which is in contact with the exposed surface of the second semiconductor layer, and the remaining part of which is in contact with the exposed surface of the second semiconductor layer; forming a third semiconductor layer by laminating it on the covering insulating film; and the first semiconductor layer;
forming separate metal electrodes in respective contact with a third semiconductor layer.