JPH036861A - Epitaxial gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To provide a low gate extraction resistance necessary for improving a maximum turn-off current without variation by a method wherein a high impurity concentration first conductivity type layer is formed on the side and bottom surface of a recess surrounding a first conductivity type epitaxial layer. CONSTITUTION:A P<++>-type diffused layer 10 is formed on the side and bottom surface of a recess which is formed by etching so as to surround an island shape epitaxial layer 4. Even if there is variation in the surface impurity concentration of a P<+>-type base layer 3 exposed in the bottom of the recess or the P<->-type epitaxial layer remains owing to the variation in etching for forming the recess, a high impurity concentration gate extraction current path can be formed by the diffusion of the P<++>-type layer, so that a low gate impedance can be maintained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an emitter layer of a second conductivity type distributed on a base layer of a first conductivity type on which a gate electrode is provided, using an epitaxial technique. Epitaxial gate turn-off formed through a layer of first conductivity type with low impurity 1 degree
(GTO) Regarding Cyrisk.

[Conventional technology]

It is desired that the GTO thyristor has a large maximum control current. In general, in order to improve the maximum control current of GTO Cyrisk, there is a method to reduce the gate impedance or a method to increase the reverse withstand voltage between the gate and cathode so that the reverse bias voltage applied between the gate and cathode can be increased at turn-off. It is being In a GTO thyristor in which an n emitter 1 p base is formed by a diffusion method, there is a mutually contradictory relationship between the reverse breakdown voltage between the gate and cathode and the gate impedance.

That is, in order to reduce the gate impedance, the concentration of the p base layer in the gate part must be high.However, in order to increase the reverse breakdown voltage between the gate and cathode, the concentration of the p base layer must be low. In order to solve these conflicting characteristics, an epitaxial GTO thyristor has been devised in which a low concentration p- layer is provided between a p base layer and an n emitter layer by epitaxial technology.

The structure of this epitaxial GTO thyristor will be explained below with reference to the drawings. A conventional epitaxial GTO thyristor has a cross-sectional structure as shown in FIG. p” base layer 3
．． p-epitaxial base IIW4. It has an n-emitter layer 5 and is formed as a number of island-like segments surrounded by an n-emitter layer 5 and a p'' epitaxial base layer 4p. An anode electrode 6 and a cathode electrode 7 are respectively deposited and are connected to the respective main terminals, for example via a pressurized contact electrode body.
Gate 1i pole 8 is deposited. Note that the side surfaces of the island segments are covered with an oxide film 9 as a protective film.

In such an epitaxial GTO thyristor, when the voltage of the anode electrode 6 is positive with respect to the cathode electrode 7, when a current flows into the gate 1i pole 8 between the cathode electrode 7 and the gate electrode 8, the epitaxial GTO thyristor changes from the OFF state to the ON state. On the other hand, when the current is extracted from the gate electrode 8, the on state changes to the off state.

[Problem to be solved by the invention]

In the epitaxial GTO cyrisk as described above, p
- Since the n-emitter layer 5 is provided on the epitaxial base N4, the impurity concentration at the gate-cathode junction is low, and the reverse breakdown voltage is increased from 20-30V to 100-1
It can be improved approximately 5 times to 50 V. This means that the reverse bias applied between the gate and cathode can be increased to about five times that of conventional elements.
Therefore, the ability to pull out from the gate is improved five times. However, since the concentration of the p base layer 4 immediately below the n emifter layer 5 is lower than that of the p-base layer of the conventional element, the impedance of that portion becomes larger than that of the conventional element. Therefore, it is necessary to draw out the 1i current from the gate at turn-off through the p-diffusion base layer 3 having a high width of γ]. This p' diffusion base layer 3 has an impurity concentration distribution due to diffusion, and the impurity concentration is high near the boundary with the p- epitaxial base layer 4.
Therefore, if the impurity level of the p layer 3 is not uniformly etched during gate etching, the gate impedance will vary and the maximum turn-off current will be significantly impaired.

With conventional gate etching technology, when performing 30-etching, an etching variation of about 5 fm occurs on a 4-inch wafer, causing variation in gate impedance, and leaving all of the p-low concentration epitaxial N4 unetched. The situation was unavoidable. In particular, there was a problem in that if the p-epitaxial layer 4 remained, the gate impedance would rise dramatically.

An object of the present invention is to solve the above-mentioned problems and provide an epitaxial GTO silicone which can uniformly form a small gate pull-out resistance necessary for improving the maximum turn-off current.

[Means to solve the problem]

To achieve the above object, the present invention provides gate t8i
an island-like low impurity concentration third conductive layer surrounded by a recess with a depth that reaches the first conductive type base layer on the opposite side of the second conductive type base layer of the first conductive type base layer provided with i. The epitaxial layer has an epitaxial layer with 1! ! In an epitaxial GTO thyristor in which an emitter layer of the second conductivity type is often formed, high impurity 1 is added to the side and bottom surfaces of the recess surrounding the first conductivity type epitaxial layer.
It is assumed that the first conductivity type layer is formed.

[Function] The high impurity concentration first conductivity type formed on the side and bottom surfaces of the recess surrounding the island-shaped low impurity concentration first conductivity type epitaxial layer becomes a path for the gate extraction current, and even if the etching depth of the recess is uneven. Low gate impedance can be ensured even if

On the other hand, the pn junction between the base of the first conductivity type and the emitter of the second conductivity type is between the low impurity concentration first conductivity type epitaxial layer and the second conductivity type emitter layer selectively formed on the surface thereof. Because it exists in 61, the high reverse voltage resistance is sufficient! Can be maintained.

〔Example〕

FIG. 1 shows a cross-sectional structure of an epitaxial GTO silicone according to an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. In this case as well, the p-epitaxial base layer 4 is formed as a large number of island-like segments surrounded by the p4 base layer 3, as in the case of Cyrisk in FIG.
An n-type emitter N5 is provided on the surface thereof. Therefore, the n-emitter layer 5 is surrounded by the p-epitaxial base layer 4, and the pn junction formed therebetween has a high reverse breakdown voltage. The difference from the silicon risk shown in FIG. 2 is that the p'' diffusion layer 1 is shown with diagonal lines on the side and bottom surfaces of the recess formed by etching surrounding the epitaxial layer 14 in an island shape.
0 is provided. This p°゛ diffusion layer is
It is formed by selective diffusion using a known self-alignment method in which the oxide film mask that protects the cathode segment is used as is when etching the periphery of the island cathode segment to form a recess. Even if there are variations in the depth of etching to form the recesses, resulting in variations in the surface impurity concentration of the p base layer at the bottom of the recesses, or even if a p- epitaxial layer remains, the diffusion of this p'' layer will result in high etching. A path for gate extraction current with an impurity concentration is formed, and a low gate impedance is ensured.Although the above example describes a GTO thyristor in which a gate electrode is provided in the p base layer, a gate electrode is provided in the n base layer. The present invention can be implemented in the same manner with respect to the provided epitaxial layer GTO thyristor.

〔Effect of the invention〕

According to the present invention, an epitaxial base layer with a low impurity concentration is interposed between the base layer of the first conductivity type and the emitter layer of the second conductivity type, thereby reducing the reverse breakdown voltage between the gate electrode and the adjacent main electrode. A high impurity concentration layer of the second conductivity type is provided on the side and bottom surfaces of the recess surrounding the island-like epitaxial layer of epitaxial GTO silice, which is approximately five times the size of the device, and serves as a path for the extraction current to the gate electrode. Ebikukisha/l/ has approximately three times the capacity of conventional elements.
It became possible to obtain a CTO thyristor.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of an epitaxial GTo silisk according to an embodiment of the present invention, and Fig. 2 is a sectional view of a conventional epitaxial CTO.
FIG. 3 is a cross-sectional view of a thyristor. 1: p emitter layer, 220 base layer, 3: p base layer 4: p-epitaxial base layer, 5: n emitter layer,
6: anode t8i, 7: cathode electrode, 8: gate electrode, 1o:p'' diffusion layer.

Claims (1)

[Claims] 1) An island-like low impurity concentration island surrounded by a recess with a depth reaching the first conductivity type base layer on the opposite side of the second conductivity type base layer where the gate electrode is provided. In a device having an epitaxial layer of the first conductivity type and in which an emitter layer of the second conductivity type is selectively formed on the surface of the epitaxial layer, high impurities are present on the side and bottom surfaces of the recess surrounding the epitaxial layer of the first conductivity type. An epitaxial gate turn-off thyristor characterized in that a concentration first conductivity type layer is formed.